AR0134CS_16 Datasheet, PDF (11/38 Pages) ON Semiconductor – 1/3-Inch 1.2 Mp CMOS Digital Image Sensor

AR0134CS: 1/3-Inch 1.2 Mp CMOS Digital Image Sensor
Configuration and Pinout
Table 3: Pin Descriptions - 63-Ball iBGA Package
Name
SLVS0_N
SLVS0_P
SLVS1_N
SLVS1_P
STANDBY
VDD_PLL
SLVSC_N
SLVSC_P
SLVS2_N
SLVS2_P
VAA
EXTCLK
VDD_SLVS
SLVS3_N
SLVS3_P
DGND
VDD
AGND
SADDR
SCLK
SDATA
VAA_PIX
LINE_VALID
FRAME_VALID
PIXCLK
FLASH
VDD_IO
DOUT8
DOUT9
DOUT10
DOUT11
TEST
DOUT4
DOUT5
DOUT6
DOUT7
TRIGGER
OE_BAR
DOUT0
DOUT1
DOUT2
DOUT3
iBGA Pin
A2
A3
A4
A5
A8
B1
B2
B3
B4
B5
B7, B8
C1
C2
C3
C4
C5, D4, D5, E5, F5, G5, H5
A6, A7, B6, C6, D6
C7, C8
D1
D2
D3
D7, D8
E1
E2
E3
E4
E6, F6, G6, H6, H7
F1
F2
F3
F4
F7
G1
G2
G3
G4
G7
Type
Output
Output
Output
Output
Input
Power
Output
Output
Output
Output
Power
Input
Power
Output
Output
Power
Power
Power
Input
Input
I/O
Power
Output
Output
Output
Output
Power
Output
Output
Output
Output
Input
Output
Output
Output
Output
Input
G8
Input
H1
Output
H2
Output
H3
Output
H4
Output
Description
HiSPi serial data, lane 0, differential N.
HiSPi serial data, lane 0, differential P.
HiSPi serial data, lane 1, differential N.
HiSPi serial data, lane 1, differential P.
Standby-mode enable pin (active HIGH).
PLL power.
HiSPi serial DDR clock differential N.
HiSPi serial DDR clock differential P.
HiSPi serial data, lane 2, differential N.
HiSPi serial data, lane 2, differential P.
Analog power.
External input clock.
HiSPi power. (May leave unconnected if parallel interface is used)
(Unsupported) HiSPi serial data, lane 3, differential N.
(Unsupported) HiSPi serial data, lane 3, differential P.
Digital GND.
Digital power.
Analog GND.
Two-Wire Serial address select.
Two-Wire Serial clock input.
Two-Wire Serial data I/O.
Pixel power.
Asserted when DOUT line data is valid.
Asserted when DOUT frame data is valid.
Pixel clock out. DOUT is valid on rising edge of this clock.
Control signal to drive external light sources.
I/O supply power.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output (MSB)
Manufacturing test enable pin (connect to DGND).
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
Exposure synchronization input. (Connect to DGND if HiSPi interface is
used)
Output enable (active LOW).
Parallel pixel data output (LSB)
Parallel pixel data output.
Parallel pixel data output.
Parallel pixel data output.
AR0134CS/D Rev. 8, Pub. 1/16 EN
11
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