TDA8296 Datasheet, PDF (74/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
14. Test information
14.1 Boundary scan interface (“IEEE Std. 1149.1”)
The TDA8296 implements a boundary scan architecture to allow access to, and control of,
board test support features within integrated circuits through a TAP. The TAP controller is
a synchronous state machine that controls the sequence of operations on the TAP
circuitry when the TMS signal changes. All state transitions occur on the basis of the TMS
value on the rising edge of TCK. The instruction register is a shift register based design. It
decodes the test to be performed and/or the test data register to be accessed. The
instructions are shifted into the register through the TDI and are latched as the current
instruction at the completion of the shifting process. The TDA8296 boundary scan
architecture includes: a TAP controller, a scannable instruction register and three
scannable test data registers: a boundary scan register, a device ID register, and a
bypass register.
The supported instructions are: EXTEST, IDCODE, SAMPLE, INTEST, CLAMP, HIGHZ
and BYPASS.
The boundary scan register is composed of 16 cells (see Table 67). Each cell is
associated either to an input pad, an output pad, a bidirectional pad or to the bidirectional
or 3-state command itself. All cells are of ‘observe and control’ type.
The device ID register is a 32-bit identification register that is included in the scan register
itself and contains the ID number. It is a fixed value that identifies the chip.
ID number structure is:
ID version [3:0] = 1h
ID part number [15:0] = 224Ch
ID manufacturer [11:1] = 015h
ID mandatory [0] = 1h
IDCODE [31:0] = 1224 C02Bh
When the boundary scan function is not used, please connect the four dedicated input
pins (TRST_N, TCK, TDI and TMS) to GND.
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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