TDA8296 Datasheet, PDF (47/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
For optimum performances, the following relations must be respected:
• 275 MHz ≤ f_VCO ≤ 550 MHz
• 4 kHz ≤ f_i / N ≤ 150 MHz
9.3.18 GPIOs
In the TDA8296, three general purpose input/outputs are implemented.
Table 54. GPIOREG_0 register (address 44h) bit description
Legend: * = default value.
Bit Symbol
Access Value Description
7 to 4 GP1_CF[3:0] R/W
It determines how the general purpose pin GPIO1 is
configured.
0000
The GPIO1 pin is in Input mode. The input value is
stored in GP1_VAL.
0001*
The GPIO1 pin is in Open-drain mode. The output
value is determined by GP1_VAL.
0011
The GPIO1 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO1 pin is in Output mode. HVPLL signals are
delivered. The HVPLL signal is chosen according to
Table 56.
XXXX
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I²C-bus feed-through like described in
Table 55.
3 to 0 GP0_CF[3:0] R/W
It determines how the general purpose pin GPIO0 is
configured.
0000
The GPIO0 pin is in Input mode. The input value is
stored in GP0_VAL.
0001
The GPIO0 pin is in Open-drain mode. The output
value is determined by GP0_VAL.
0011
The GPIO0 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011*
The GPIO0 pin is in Output mode. HVPLL signals are
delivered. The HVPLL signal is chosen according to
Table 56.
Table 55. GPIOREG_1 register (address 45h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7
I2CSW_EN R/W 1*
When I2CSW_EN = 1, GPIO1 and GPIO2 are
6
I2CSW_ON R/W 0*
configured as an I²C-bus feed-through independently of
the GP1_CF and GP2_CF value. When
I2CSW_ON = 0, the feed-through switch is open, and
GPIO1 and GPIO2 are in 3-state. When the switch is
closed (I2CSW_ON = 1), the I²C-bus clock and data
signals (SCL and SDA) are available on the GPIO1 and
GPIO2 pins.
5 and 4 -
R/W 00* not used
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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