TDA8296 Datasheet, PDF (44/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
Table 47. CLB_STDBY register (address 30h) bit description …continued
Legend: * = default value.
Bit Symbol Access Value Description
1
STDBY R/W
When STDBY is set to logic 1, the chip enters in Standby
mode, and its power consumption is reduced. The IF AGC pin
is set to high-ohmic. The default value is logic 0, which means
that the chip is active.
0*
Normal mode
1
Standby mode
0
CLB R/W
This signal clears the TDA8296 through the I²C-bus interface
(software reset). To activate the reset, just write CLB = 0. This
software reset will not affect the content of the registers.
0
activate soft reset
1*
normal operation
9.3.15 ADC control
In the TDA8296 a 12-bit ADC is implemented sampling with a 54 MHz clock (27 MHz
optional).
Table 48. ADC_CTL register (address 33h) bit description
Legend: * = default value.
Bit Symbol Access Value Description
7 to 4 -
R/W 0010* reserved, must be set to logic 0010
3
DCIN
R/W
The input signal of the ADC can be either AC coupled by
means of two capacitors or connected directly to the inputs
(DC coupled).
0*
AC coupling
1
DC coupling
2
-
R/W 1*
reserved, must be set to logic 1
1
SLEEP R/W
When HIGH, SLEEP sets the ADC into its Sleep mode. Both
bias current and clock are switched off. In this mode, the
current consumption is reduced by a factor of 6. The
reference circuit will remain active in order to guarantee a fast
recovery from Sleep mode.
0*
Normal mode
1
ADC Sleep mode
0
PD_ADC R/W
When HIGH, PD_ADC sets the ADC into its Power-down
mode. All internal currents are switched off. In this mode, the
current consumption is near zero (leakage current only).
0*
Normal mode
1
ADC Power-down mode
Table 49. ADC_CTL_2 register (address 34h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 3 -
R/W 0000 0* not used
2 and 1 -
R/W 10*
reserved, must be set to logic 10
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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