TDA8296 Datasheet, PDF (49/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
9.3.19 Special equalizer functions for group delay and video (CVBS)
To realize special customer demands or accurate compensation of the tuner influence,
the TDA8296 has got freely programmable equalizers for the group delay and video
(CVBS) response.
In Table 58 the programming of the group delay equalizer is explained, in Table 60 the
programming of the video equalizer. For each equalizer type an example is given.
Table 58. GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) register (address 4Bh to
52h) bit description
Legend: * = default value^[1].
Address Register
Bit
Symbol
Access Value
4Bh
GD_EQ_SECT1_C1 7 to 0 GD_EQ_SECT1_C1[7:0]
R/W 00h*
4Ch
GD_EQ_SECT1_C2 7 to 0 GD_EQ_SECT1_C2[7:0]
R/W 00h*
4Dh
GD_EQ_SECT2_C1 7 to 0 GD_EQ_SECT2_C1[7:0]
R/W 00h*
4Eh
GD_EQ_SECT2_C2 7 to 0 GD_EQ_SECT2_C2[7:0]
R/W 00h*
4Fh
GD_EQ_SECT3_C1 7 to 0 GD_EQ_SECT3_C1[7:0]
R/W 00h*
50h
GD_EQ_SECT3_C2 7 to 0 GD_EQ_SECT3_C2[7:0]
R/W 00h*
51h
GD_EQ_SECT4_C1 7 to 0 GD_EQ_SECT4_C1[7:0]
R/W 00h*
52h
GD_EQ_SECT4_C2 7 to 0 GD_EQ_SECT4_C2[7:0]
R/W 00h*
[1] Don’t care if GD_EQ_CTRL = 0; see Table 23.
Remark: The group delay equalizer consists of four cascaded all-pass Infinite Impulse
Response (IIR) sections of second order (8th order in sum). The transfer function H(z) of
one section is as follows, while the sampling rate is 13.5 MHz:
H(z) = -----^b---²----+-----^b---¹----^×-----^z--^–---¹----+----^z---^–--²------
1 + b₁ × z^–1 + b₂ × z^–2
GD_EQ_SECTx_C1 and GD_EQ_SECTx_C2 (x = 1 to 4) are defining the linear and
square coefficient of each section, i.e. GD_EQ_SECTx_C1 = b₁ and
GD_EQ_SECTx_C2 = b₂. The coefficients are in signed fixed-point format, the
representation is in two’s complement. There is one sign bit, one magnitude bit and
6 fractional bits. Each fractional bit represents an inverse power of two, so that the highest
value for a coefficient is 2⁰ + 2^−1 + ... + 2^−6 = 2¹ − 2^−6 = 1.984375. The binary
representation for this value is 01.11 1111 (= 7Fh) and all bits except the sign bit are
logic 1. As two’s complement is chosen, the lowest value for a coefficient is −2, which is
10.00 0000 (= 80h) in the binary representation. So, for the lowest possible value, only the
sign bit is logic 1. The shown default values for GD_EQ_SECTx_C1 and
GD_EQ_SECTx_C2 (x = 1 to 4) implement a flat equalizer response.
Example of Table 58: If e.g. a flat group delay response up to 4 MHz and −70 ns from
4.43 MHz to 5 MHz on the CVBS signal is wanted, one might realize a characteristic like
shown in Figure 17.
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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