TDA8296 Datasheet, PDF (34/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
9.3.10 V-sync adjustment
Table 29. V_SYNC_DEL register (address 1Ch) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 and 6 VS_WIDTH[1:0] R/W
VS_WIDTH determines the width (in horizontal
lines) of the V-sync gating pulse (needed for gating
of tuner RF AGC2)
00
width 1 line (64 μs)
01*
width 2 lines
10
width 4 lines
11
width 16 lines
5
VS_POL
R/W
VS_POL determines the polarity of the V-sync
pulse: if VS_POL = 1, the first edge of the pulse is
positive, else negative.
0
first edge negative
1*
first edge positive
4 to 0 VS_DEL[4:0] R/W
VS_DEL determines the first edge position of the
output V-sync pulse compared to the beginning of
the vertical blanking interval:
pulse_position = (VS_DEL – 12) lines
0Fh*
first edge 3 lines after beginning of vertical
interval
9.3.11 CVBS settings
Table 30. CVBS_SET register (address 1Dh) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 and 6 -
R/W 00* not used
5 and 4 -
R/W 11* must be set to logic 11 or in case of L/L-accent to 01
3
CVBS_EQ_ R/W
video equalizer mode control
CTRL
0*
mode using predefined settings like described in
Table 32
1
free programmable mode; for details
see Section 9.3.19
2
FOR_BLK R/W
when active, the video output is always blanked, e.g. for
channel change (forced blank)
0*
no action
1
video blanked
1
AUTO_BLK R/W
when active, the video output is blanked if the horizontal
line lock flag (N_H_LOCK, see Table 41) is not present
0*
auto-blanking off
1
auto-blanking on
0
-
R/W 1*
reserved, must be set to logic 1
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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