TDA8296 Datasheet, PDF (46/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
Table 51. AUDIODAC_CTL register (address 36h) bit description
Legend: * = default value.
Bit Symbol
Access Value Description
7
-
R/W 0*
reserved, must be set to logic 0
6 to 1 B_DA_S[5:0] R/W
B_DA_S modifies between 50% to 100% the full scale
DAC output current. See Section 13.3.
00 0000* minimum current setting
11 1111 maximum current setting
0
PD_DA_S R/W
When HIGH, PD_DA_S sets the sound DAC into its
Power-down mode.
0*
Normal mode
1
sound DAC Power-down mode
Table 52. DAC_REF_CLK_CTL register (address 37h) bit description
Legend: * = default value.
Bit Symbol
Access Value Description
7
-
R/W 0*
not used
6 to 1 -
R/W 10 0000* reserved, must be set to logic 10 0000
0
PD_DA_REF R/W
When HIGH, PD_DA_REF sets the reference module
into its Power-down mode.
0*
Normal mode
1
Power-down mode
9.3.17 Clock generation (PLL and crystal oscillator)
The TDA8296 implements a crystal oscillator which can be used either in Slave mode or
in Oscillator mode (see Section 13.7), and a multipurpose PLL which receives XIN as
input clock, and delivers the system clock of the IC (108 MHz).
Table 53. PLL_REG07, PLL_REG08, PLL_REG09 and PLL_REG10 register (address 3Fh to 42h) bit description
Legend: * = default value.
Address Register Bit Symbol Access Value Description
3Fh
PLL_REG07 7
-
R/W 0*
not used
6
NSEL7 R/W 0*
It programs bit 7 of the N parameter (N = NSEL + 1). N is the
PLL pre-divider. See below for bits NSEL[6:0].
5 to 0 -
R/W 00h* reserved, must be set to 00h
40h
PLL_REG08 7 to 0 MSEL[7:0] R/W 1Ah* It programs the M parameter (M = MSEL + 1). M is the PLL
feedback-divider.
41h
PLL_REG09 7 to 1 NSEL[6:0] R/W 01h* It programs bits 6 to 0 of the N parameter (N = NSEL + 1).
N is the PLL pre-divider.
0
-
R/W 0*
reserved, must be set to logic 0
42h
PLL_REG10 7 to 5 -
R/W 000* reserved, must be set to logic 000
4 to 0 PSEL[4:0] R/W
01h* It programs the P parameter (P = PSEL + 1). P is the PLL
post-divider.
The PLL output frequency (108 MHz) can be calculated with the following formula:
TDA8296
Product data sheet
f_clk(o)(PLL)
=
-^f--^V---^C---^O---
2×P
=
f_--i---×_-----M_---
N×P
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
(1)
© NXP B.V. 2011. All rights reserved.
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