TDA8296 Datasheet, PDF (54/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
12. Characteristics
Table 64. Characteristics
Power supplies 3.3 V, 1.2 V; T_amb = 25 °C; PC/SC1 for L and M = 10 dB, all others 13 dB; nominal residual picture carrier of
3 % for L/L’ , 10 % for M, 10 % for B/G, 12.5 % for D/K, 20 % for I; FM/AM modulation = 54 %, 1 kHz modulation frequency;
measured in application PCB (see Figure 22 and Figure 23) with 16 MHz crystal frequency, terminated with 75 Ω (CVBS) and
1 kΩ (SSIF/audio). Operation mode set via easy programming (Section 9.3.1), otherwise stated. Low IF input signal at -3dB
full scale, input frequencies as defined under row header IF input.
Symbol
Parameter
Conditions
Min
Typ
Max Unit
Power supply
V_DD(1V2)
supply voltage (1.2 V)
digital and analog
1.1
V_DD(3V3)
supply voltage (3.3 V)
digital and analog
3.0
I_DD(tot)(1V2)
total supply current (1.2 V)
-
I_DD(tot)(3V3)
total supply current (3.3 V)
-
P_tot
total power dissipation
default settings; f_s = 54 MHz
-
at ADC; DAC application in
accordance to Figure 23
1.2
1.3 V
3.3
3.6 V
49
-
mA
65
-
mA
270
-
mW
f_s = 54 MHz at ADC; DAC
-
application in accordance to
Figure 24
150
-
mW
Standby mode
-
5
8
mW
Digital I/Os
V_IH
HIGH-level input voltage all inputs (except pin XIN);
0.7 × V_DD(3V3) -
6.0 V
including voltage on outputs in
3-state mode
V_IL
LOW-level input voltage all inputs (except pin XIN);
-
including voltage on outputs in
3-state mode
-
0.8 V
V_OH
HIGH-level output voltage
V_OL
LOW-level output voltage
C_i
input capacitance
Master clock
source current 4 mA
sink current 4 mA
V_DD(3V3) − 0.4 -
-
-
-
-
-
V
0.4 V
5
pF
f_clk(o)(PLL)
Δf/f_clk
PLL output clock frequency
relative frequency deviation
from clock frequency
[1] _-
108
-
MHz
-
-
±200 10^−6
Reference frequency in Slave mode
f_clk(ext)
V_i(RMS)
SR_r
t_jit(cc)
C_i
external clock frequency
RMS input voltage
rising slew rate
cycle-to-cycle jitter time
input capacitance
AC coupled
external clock
RMS value
on pin XIN
-
16
-
MHz
200
250
-
mV
30
-
-
mV/ns
-
12.5
-
ps
-
3
-
pF
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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