TDA8296 Datasheet, PDF (48/87 Pages) NXP Semiconductors – Digital global standard low IF demodulator for analog TV and FM radio

NXP Semiconductors
TDA8296
Digital global standard low IF demodulator for analog TV and FM radio
Table 55. GPIOREG_1 register (address 45h) bit description …continued
Legend: * = default value.
Bit
Symbol
Access Value Description
3 to 0 GP2_CF[3:0] R/W
It determines how the general purpose pin GPIO2 is
configured.
0000
The GPIO2 pin is in Input mode. The input value is
stored in GP2_VAL.
0001*
The GPIO2 pin is in Open-drain mode. The output
value is determined by GP2_VAL.
0011
The GPIO2 pin is in Output mode. The PLL output
clock divided by two is delivered.
0100
to
1011
The GPIO2 pin is in Output mode. HVPLL signals are
delivered. The HVPLL signal is chosen according to
Table 56.
XXXX
Don’t care if I2CSW_EN = 1. Then the pad is
configured as I²C-bus feed-through.
Table 56. HVPLL signal configuration
HVPLL_BUS bit
GPx_CF[3:0] = 1011
GPx_CF[3:0] = 1010
GPx_CF[3:0] = 1001
GPx_CF[3:0] = 1000
GPx_CF[3:0] = 0111
GPx_CF[3:0] = 0110
GPx_CF[3:0] = 0101
GPx_CF[3:0] = 0100
Signal
V_SYNC
H_SYNC
NOISE_DET
MAC_DET
FIDT
V_LOCK
F_H_LOCK
N_H_LOCK
Table 57. GPIOREG_2 register (address 46h) bit description
Legend: * = default value.
Bit
Symbol
Access Value Description
7 to 5 -
R/W 000* reserved, must be set to logic 000
4 and 3 -
R/W 00* not used
2
GP2_VAL
R/W 1*
GP2_VAL controls the value of the pin GPIO2 when
GP2_CF[3:0] = 0001. When GP2_CF[3:0] = 0000,
GPIO2 is an input pin which value can be read
through the I²C-bus stored in GP2_VAL.
1
GP1_VAL
R/W 1*
GP1_VAL controls the value of the pin GPIO1 when
GP1_CF[3:0] = 0001. When GP1_CF[3:0] = 0000,
GPIO1 is an input pin which value can be read
through the I²C-bus stored in GP1_VAL.
0
GP0_VAL
R/W 1*
GP0_VAL controls the value of the pin GPIO0 when
GP0_CF[3:0] = 0001. When GP0_CF[3:0] = 0000,
GPIO0 is an input pin which value can be read
through the I²C-bus stored in GP0_VAL.
TDA8296
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 3 March 2011
© NXP B.V. 2011. All rights reserved.
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