TDA8025 Datasheet, PDF (20/38 Pages) NXP Semiconductors – IC card interface

NXP Semiconductors
TDA8025
IC card interface
• V_DD(INTF) falling
• Overheating
Fault detection monitors two different situations (see Figure 15 on page 21):
1. Outside card sessions, pin CMDVCCN is HIGH: pin OFFN is LOW if the card is not in
the reader and HIGH if the card is in the reader. Any supply voltage drop on
V_DD(INTREGD) or V_DD(INTF) is detected by the supply supervisor. This generates an
internal power-on reset pulse but does not act upon the pin OFFN signal. The card is
not powered-up and as such short-circuits and overheating are not detected.
2. Within card sessions, pin CMDVCCN is LOW: when pin OFFN falls LOW, the fault
detection circuit triggers the automatic emergency deactivation sequence (see
Figure 14). When the system controller resets pin CMDVCCN to HIGH, after the
deactivation sequence, pin OFFN is rechecked. If the card is still present, pin OFFN
returns to HIGH. This check identifies the fault as either a hardware problem or a card
removal incident.
On card insertion or removal, bouncing can occur in the PRES and/or PRESN signals.
This depends on the type of card presence switch in the connector (normally open or
normally closed) and the mechanical characteristics of the switch. To correct for this, a
debouncing feature is integrated in to the TDA8025. This feature operates at a typical
duration of 640 × (¹â„_fosc(int)low). See Figure 15 for an overview of the debouncing feature.
Remark: f_osc(int)low is the low frequency (or inactive) mode of the defined f_osc(int)
parameter.
On card insertion, pin OFFN goes HIGH after the debouncing time has elapsed. When the
card is extracted, the automatic card deactivation sequence is performed on the first true
or false transition on pin PRESN or pin PRES. After this pin OFFN goes LOW.
OFFN
PRESN
RST
CLK
I/O
V_CC
XTAL
OSCINT
high frequency
t10
t12
t13
t14
t_deact
low frequency
Fig 14. Emergency deactivation sequence after card removal
001aai971
TDA8025_1
Product data sheet
Rev. 01 — 6 April 2009
© NXP B.V. 2009. All rights reserved.
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