TDA8025 Datasheet, PDF (17/38 Pages) NXP Semiconductors – IC card interface

NXP Semiconductors
TDA8025
IC card interface
CMDVCCN
XTAL1
V_CC
I/O
ATR
CLK
RSTIN
> 200 ns
RST
I/OUC
OSCINT
low frequency
t0 t1 = t2
t4
t_d(start)
high frequency
t_d(end) = t_act
001aai968
Fig 11. Activation sequence: CLK not controlled by pin RSTIN and with an external clock
connected to pin XTAL1
8.7 Active mode
When the activation sequence has finished, the TDA8025 is in active mode. This mode
enables data exchange between the card and the microcontroller using the input and
output lines.
Depending on the layout and application test conditions, line C2 could become polluted
with high frequency noise from line C3. For example, due to an additional 1 pF
capacitance between lines C2/C3 and/or lines C2/C7. It is recommended that a 100 pF
capacitor is added between line C2 and pin CGND, if this occurs.
When building the application, the following recommendations should be adhered to:
• Keep track C3 as far away as possible from other tracks.
• Keep the connection between pin CGND and line C5 straight. The two capacitors on
line C1 should be connected to this ground track.
• Do not use ground loops between CGND and GND.
Following these layout recommendations will ensure that noise remains within the
specifications and jitter on line C3 is less than 100 ps.
TDA8025_1
Product data sheet
Rev. 01 — 6 April 2009
© NXP B.V. 2009. All rights reserved.
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