PC87309 Datasheet, PDF (88/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Parallel Port (Logical Device 1)
A “Demand DMA” feature reduces system overhead
caused by DMA data transfers. When this feature is en-
abled by bit 6 of the PP Config0 register at second level off-
set 05h, it prevents servicing of DMA requests until after
four have accumulated and are held pending. See “Bit 6 -
Demand DMA Enable” on page 94.
Writing into a full FIFO, and reading from an empty FIFO,
are ignored. The written data is lost, and the read data is un-
defined. The FIFO empty and full status bits are not affected
by such accesses.
Some registers are not accessible in all modes of operation,
or may be accessed in one direction only. Accessing a non
accessible register has no effect. Data read is undefined;
data written is ignored; and the FIFO does not update. The
SPP registers (DTR, STR and CTR) are not accessible
when the ECP is enabled.
To improve noise immunity in ECP cycles, the state ma-
chine does not examine the control handshake response
lines until the data has had time to switch.
In ECP modes:
q _{DATAR replaces DTR of SPP/EPP}
q _{DSR replaces STR of SPP/EPP}
q _{DCR replaces CTR of SPP/EPP}
4.5.2 Second Level Offsets
The EIR, EDR, and EAR registers support enhanced con-
trol and status features. When bit 4 of the Parallel Port Con-
figuration register is 1 (as described in Section 2.6
"SUPERI/O PARALLEL PORT CONFIGURATION REGIS-
TER (LOGICAL DEVICE 1)" on page 30), EIR and EDR
serve as index and data registers, respectively.
EIR and EDR at offsets 403 and 404, respectively, access
the control registers (Control0, Control2, Control4 and PP
Config0) at second level offsets 00h, 02h, 04h and 05h, re-
spectively. These control registers are functional only. Ac-
cessing these registers is possible when bit 4 of the
SuperI/O Parallel Port Configuration register at index F0h of
Logical Device 1 is 1 and when bit 2 or 10 of the base ad-
dress is 1.
4.5.3 ECP Data Register (DATAR)
The ECP Data Register (DATAR) register is the same as
the DTR register (see Section 4.2.2 "SPP Data Register
(DTR)" on page 80), except that a read always returns the
values of the PD7-0 signals instead of the register latched
data.
Bits 7-5 of ECR = 000 or 001
76543210
ECP Data Register
0 0 0 0 0 0 0 0 Reset
(DATAR)
Offset 000h
Required
D0
D1
D2
D3
D4
D5
Data Bits
D6
D7
4.5.4 ECP Address FIFO (AFIFO) Register
The ECP Address FIFO Register (AFIFO) is write only. In
the forward direction (when bit 5 of DCR is 0) a byte written
into this register is pushed into the FIFO and tagged as a
command.
Reading this register returns undefined contents. Writing to
this register in a backward direction (when bit 5 of DCR is 1)
has no effect and the data is ignored.
Bits 7-5 of ECR = 011
7 6 5 4 3 2 1 0 _{ECP Address Register}
0 0 0 0 0 0 0 0 Reset
(AFIFO)
Offset 000h
Required
A0
A1
A2
A3
A4
A5
Address Bits
A6
A7
4.5.5 ECP Status Register (DSR)
This read-only register displays device status. Writes to this
DSR have no effect and the data is ignored.
This register should not be confused with the DSR register
of the Floppy Disk Controller (FDC).
76543210
ECP Status Register
1 1 1 Reset
(DSR)
Offset 001h
1 1 Required
EPP Time-Out Status
Reserved
Reserved
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
Bits 0 - EPP Time-Out Status
In EPP modes only, this is the time-out status bit. In all
other modes this bit has no function and has the con-
stant value 1.
This bit is cleared when an EPP mode is enabled.
Thereafter, this bit is set to 1 when a time-out occurs in
an EPP cycle and is cleared when STR is read.
In EPP modes:
0 - An EPP mode is set. No time-out occurred since
STR was last read.
1: Time-out occurred on EPP cycle (minimum of 10
µsec). (Default)
Bits 2,1: Reserved
These bits are reserved and are always 1.
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