PC87309 Datasheet, PDF (67/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

The Floppy Disk Controller (FDC) (Logical Device 0)
TABLE 3-18. SK Effect on READ DELETED DATA
Command
Skip
Control
(SK)
Data
Type
Sector
Read?
Control
Mark Bit 6
of ST2
Result
0
Normal Y
0 Deleted Y
1
Normal N
1 Deleted Y
1
No More
Sectors Read
0
Normal
Termination
1
Sector Skipped
0
Normal
Termination
Result Phase
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
3.7.12 The READ ID Command
The READ ID command finds the next available address
field and returns the ID bytes (track number, head number,
sector number, bytes-per-sector code) to the microproces-
sor in the result phase.
The controller reads the first ID Field header bytes it can
find and reports these bytes to the system in the result
bytes.
Command Phase
7
6
5
4
3
2
1
0
0 MFM 0
0
1
0
1
0
X
X
X
X
X HD DS1 DS0
Second Command Phase Byte
See “Second Command Phase Byte” on page 57 for a
description of the Drive Select (DS1,0) and Head Select
(HD) bits.
Execution Phase
There is no data transfer during the execution phase of this
command. An interrupt is generated when the execution
phase is completed.
The READ ID command does not perform an implied seek.
After waiting the Delay Before Processing time, the control-
ler starts the data separator and waits for the data separator
to find the address field of the next sector. If an error condi-
tion occurs, the Interrupt Code (IC) bits in ST0 are set to ab-
normal termination (01), and the controller enters the result
phase.
Possible errors are:
q _{The microprocessor aborted the command by writing to}
the FIFO.
If there is no disk in the drive, the controller gets stuck.
The microprocessor must then write a byte to the FIFO
to advance the controller to the result phase.
q _{Two pulses of the INDEX signal were detected since the}
search began, and no Address Mark (AM) was found.
When the Address Mark (AM) is not found, the Missing
Address Mark bit (bit 0) is set in ST1. Section 3.5.2 on
page 49 describes the bits of ST1.
Result Phase
7
6
5
4
3
2
1
0
Result Phase Status Register 0 (ST0)
Result Phase Status Register 1 (ST1)
Result Phase Status Register 2 (ST2)
Track Number
Head Number
Sector Number
Bytes-Per-Sector Code
After the last command phase byte is written, the controller
waits the Delay Before Processing time (see TABLE 3-24
on page 74) for the selected drive. During this time, the
drive motor must be turned on by enabling the appropriate
drive and motor select disk interface output signals via the
bits of the Digital Output Register (DOR). See Section 3.3.3
on page 39.
First Command Phase Byte, Opcode
See “Bit 6 - Modified Frequency Modulation (MFM)” on
page 57.
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