PC87309 Datasheet, PDF (177/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Device Specifications
FIFO Mode
SIN
Sample Clock
Trigger
Level
Interrupt
LSI
Interrupt
RD
(RD LSR)
RD
(RD RBR)
Data (5-8)
Stop
Note
t_SINT
t_RINT
Active
t_RAI2
Active
Note:
If SCR0 = 1, then t_SINT = 3 RCLKs. For a time-out interrupt, t_SINT = 8 RCLKs.
Time-Out Mode
SIN
Sample Clock
Time-Out or
Trigger Level
Interrupt
LSI Interrupt
RD
(RD LSR)
RD
(RD RBR)
Stop
Note
t_SINT
Top Byte of FIFO
t_SINT
t_RINT
Active
Active
Previous Byte
Read From FIFO
Note:
If SCR0 = 1, then t_SINT = 3 RCLKs. For a time-out interrupt, t_SINT = 8 RCLKs
t_RAI3
Active
(FIFO at
or above
Trigger
Level)
(FIFO
Below
Trigger
Level)
(FIFO at
or above
Trigger
Level)
(FIFO
Below
Trigger
Level)
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