PC87309 Datasheet, PDF (141/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Enhanced Serial Port - UART1 (Logical Device 3)
TABLE 6-3. Non-Extended Mode Interrupt Priorities
EIR Bits
3210
0001
0110
0100
1100
0010
0000
Priority
Level
−
Highest
Second
Second
Third
Fourth
Interrupt Set and Reset Functions
Interrupt Type
Interrupt Source
Interrupt Reset Control
None
None
−
Line Status Parity error, framing error, data overrun Read Line Status Register (LSR).
or break event
Receiver High Receiver Holding Register (RXD) full, or Reading the RXD or, RX_FIFO level
Data Level RX_FIFO level equal to or above
drops below threshold.
Event
threshold.
RX_FIFO Time- At least one character is in the
Reading the RXD port.
Out
RX_FIFO, and no character has been
input to or read from the RX_FIFO for 4
character times.
Transmitter Low Transmitter Holding Register or
Data Level TX_FIFO empty.
Event
Reading the EIR Register if this
interrupt is currently the highest
priority pending interrupt, or writing
into the TXD port.
Modem Status Any transition on CTS, DSR or DCD or a Reading the Modem Status Register
low to high transition on RI.
(MSR).
Event Identification Register (EIR), Extended Mode
In Extended mode, each of the previously prioritized and
encoded interrupt sources is broken down into individual
bits. Each bit in this register acts as an interrupt pending
flag, and is set to 1 when the corresponding event occurred
or is pending, regardless of the IER register bit setting.
Extended Mode, Read Cycles
76543210
Event Identification
0 0 0 0 0 0 0 1 Reset
Register (EIR)
Bank 0,
Required
Offset 02h
RXHDL_EV
TXLDL_EV
LS_EV or TXHLT_EV
MS_EV
Reserved
TXEMP-EV
Reserved
Reserved
Bit 0 - Receiver High-Data-Level Event (RXHDL_EV)
When FIFOs are disabled, this bit is set to 1 when a
character is in the Receiver Holding Register.
When FIFOs are enabled, this bit is set to 1 when the
RX_FIFO is above threshold or an RX_FIFO time-out
has occurred.
Bit 1 - Transmitter Low-Data-Level Event (TXLDL_EV)
When FIFOs are disabled, this bit is set to 1 when the
Transmitter Holding Register is empty.
When FIFOs are enabled, this bit is set to 1 when the
TX_FIFO is below the threshold level.
Bit 2 - Line Status Event (LS_EV) or Transmitter Halted
Event (TXHLT_EV)
This bit is set to 1 when a receiver error or break condi-
tion is reported.
When FIFOs are enabled, the Parity Error(PE), Frame
Error(FE) and Break(BRK) conditions are only reported
when the associated character reaches the bottom of
the RX_FIFO. An Overrun Error (OE) is reported as
soon as it occurs.
Bit 3 - Modem Status Event (MS_EV)
In UART mode this bit is set to 1 when any of the 0 to 3
bits in the MSR register is set to 1.
Bit 4 - Reserved
Read/Write 0.
Bit 5 - Transmitter Empty (TXEMP_EV)
This bit is the same as bit 6 of the LSR register. It is set
to 1 when the transmitter is empty.
Bits 7,6 - Reserved
Read/Write 0.
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