PC87309 Datasheet, PDF (140/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Enhanced Serial Port - UART1 (Logical Device 3)
Interrupt Enable Register (IER), in the Extended Mode
See the bitmap of the Interrupt Enable Register in these
mode.
IER in Extended Mode
76543210
Interrupt Enable
0 0 0 0 0 0 0 0 Reset
Register (IER)
Bank 0,
Required
Offset 01h
RXHDL_IE
TXLDL_IE
LS_IE
MS_IE
Reserved
TXEMP_IE
Reserved
Reserved
Bit 0 - Receiver High-Data-Level Interrupt Enable
(RXHDL_IE)
Setting this bit enables interrupts when the RX_FIFO is
equal to or above the RX_FIFO threshold level, or an
RX_FIFO time out occurs.
0: Disable Receiver Data Ready interrupt. (Default)
1: Enable Receiver Data Ready interrupt.
Bit 1 - Transmitter Low-Data-Level Interrupt Enable
(TXLDL_IE)
Setting this bit enables interrupts when the TX_FIFO is
below the threshold level or the Transmitter Holding
Register is empty.
0: Disable Transmitter Low-Data-Level Interrupts (De-
fault).
1: Enable Transmitter Low-Data-Level Interrupts.
Bit 2 - Line Status Interrupt Enable (LS_IE)
Setting this bit enables interrupts on Line Status events.
0: Disable Line Status Interrupts (LS_EV) (Default)
1: Enable Line Status Interrupts (LS_EV).
Bit 3 - Modem Status Interrupt Enable (MS_IE)
Setting this bit enables the interrupts on Modem Status
events.
0: Disable Modem Status Interrupts (MS_EV) (Default)
1: Enable Modem Status Interrupts (MS_EV).
Bit 4 - Reserved
Reserved.
Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)
Setting this bit enables interrupt generation if the trans-
mitter and TX_FIFO become empty.
0: Disable Transmitter Empty interrupts (Default)
1: Enable Transmitter Empty interrupts.
Bits 7,6 - Reserved
Reserved.
6.5.3 Event Identification Register (EIR)
The Event Identification Register (EIR) and the FIFO
Control Register (FCR) (see next register description)
share the same address. The EIR is accessed during CPU
read cycles while the FCR is accessed during CPU write cy-
cles.The Event Identification Register (EIR) indicates the in-
terrupt source. The function of this register changes
according to the selected mode of operation.
Event Identification Register (EIR), Non-Extended Mode
When Extended mode is not selected (EXT_SL bit in
EXCR1 register is set to 0), this register is the same as in
the 16550.
In a Non-Extended UART mode, this module prioritizes in-
terrupts into four levels. The EIR indicates the highest level
of interrupt that is pending. The encoding of these interrupts
is shown in Table 6-3 on page 141.
Non-Extended Modes, Read Cycles
76543210
Event Identification
0 0 0 0 0 0 0 1 Reset
Register (EIR)
Bank 0,
00
Required
Offset 02h
IPF - Interrupt Pending
IPR0 - Interrupt Priority 0
IPR1 - Interrupt Priority 1
RXFT - RX_FIFO Time-Out
Reserved
Reserved
FEN0 - FIFOs Enabled
FEN1 - FIFOs Enabled
Bit 0 - Interrupt Pending Flag (IPF)
0: There is an interrupt pending.
1: No interrupt pending. (Default)
Bits 2,1 - Interrupt Priority 1,0 (IPR1,0)
When bit 0 (IPF) is 0, these bits indicate the pending in-
terrupt with the highest priority. See Table 6-3 on page
141.
Default value is 00.
Bit 3 - RX_FIFO Time-Out (RXFT)
In the 16450 mode, this bit is always 0. In the 16550
mode (FIFOs enabled), this bit is set to 1 when an
RX_FIFO read time-out occurred and the associated in-
terrupt is currently the highest priority pending interrupt.
Bits 5,4 - Reserved
Read/Write 0.
Bit 7,6 - FIFOs Enabled (FEN1,0)
0: No FIFO enabled. (Default)
1: FIFOs are enabled (bit 0 of FCR is set to 1).
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