PC87309 Datasheet, PDF (55/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

The Floppy Disk Controller (FDC) (Logical Device 0)
WLD Wildcard bit in the MODE command used to enable
or disable the wildcard byte (FFh) during scan com-
mands.
WNR Write Number controls whether to read an existing
track number or to write a new one in the SET
TRACK command.
3.7.2 The CONFIGURE Command
The CONFIGURE command controls some operation
modes of the controller. It should be issued during the ini-
tialization of the FDC after power up.
The bits in the CONFIGURE registers are set to their default
values after a hardware reset.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0 EIS FIFO POLL Threshold (THRESH)
Precompensation Track Number (PRETRK)
Third Command Phase Byte
Bits 3-0 - The FIFO Threshold (THRESH)
These bits specify the threshold of the FIFO during the
execution phase of read and write data transfers.
This value is programmable from 00h to 0Fh. A software
reset sets this value to 00 if the LOCK bit (bit 7 of the op-
code of the LOCK command) is 0. If the LOCK bit is 1,
THRESH retains its value.
Use a high value of THRESH for systems that respond
slowly and a low value for fast systems.
Bit 4 - Disable Drive Polling (POLL)
This bit enables and disabled drive polling. A software
reset clears this bit to 0.
When drive polling is enabled, an interrupt is generated
after a reset.
When drive polling is disabled, if the CONFIGURE com-
mand is issued within 500 msec of a hardware or soft-
ware reset, then an interrupt is not generated. In
addition, the four SENSE INTERRUPT commands to
clear the Ready Changed State of the four logical drives
is not required.
0: Enable drive polling. (Default)
1: Disable drive polling.
Bit 5 - Enable FIFO (FIFO)
This bit enables and disables the FIFO for execution
phase data transfers.
If the LOCK bit (bit 7 of the opcode of the LOCK com-
mand) is 0, a software reset disables the FIFO, i.e., sets
this bit to 1.
If the LOCK bit is 1, this bit retains its previous value af-
ter a software reset.
0: FIFO enabled for read and write operations.
1: FIFO disabled. (Default)
Bit 6 - Enable Implied Seeks (EIS)
This bit enables or disables implied seek operations. A
software reset disables implied seeks, i.e., clears this bit
to 0.
Bit 5 of the MODE command (Implied Seek (IPS) can
override the setting of this bit and enable implied seeks
even if they are disabled by this bit.
When implied seeks are enabled, a seek or sense inter-
rupt operation is performed before execution of the read,
write, scan, or verify operation.
0: Implied seeks disabled. The MODE command can
still enable implied seek operations. (Default)
1: Implied seeks enabled for read, write, scan and
VERIFY operations, regardless of the value of the
IPS bit in the MODE command.
Fourth Command Phase Byte, Bits 7-0,
Precompensation Track Number (PRETRK)
This byte identifies the starting track number for write
precompensation. The value of this byte is programma-
ble from track 0 (00h) to track 255 (FFh).
If the LOCK bit (bit 7 of the opcode of the LOCK com-
mand) is 0, after a software reset this byte indicates
track 0 (00h).
If the LOCK bit is 1, PRETRK retains its previous value
after a software reset.
Execution Phase
Internal registers are written.
Result Phase
None.
3.7.3 The DUMPREG Command
The DUMPREG command supports system run-time diag-
nostics, and application software development and debug-
ging.
DUMPREG has a one-byte command phase (the opcode)
and a 10-byte result phase, which returns the values of pa-
rameters set in other commands. See the commands that
set each parameter for a detailed description of the param-
eter.
Command Phase
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
0
Execution Phase
Internal registers read.
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