PC87309 Datasheet, PDF (83/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Parallel Port (Logical Device 1)
or EPP Data Registers 0-3 (DATA0-3), EPP modes behave
like SPP Extended mode, except for the interrupt, which is
pulse triggered instead of level triggered.
Bit 7 of STR (BUSY status) must be set to 1 before writing
to DTR in EPP modes to ensure data output to PD7-0.
The enhanced parallel port monitors the IOCHRDY signal
during EPP cycles. If IOCHRDY is driven low for more then
10 µsec, an EPP time-out event occurs, which aborts the
cycle by asserting IOCHRDY, thus releasing the system
from a stuck EPP peripheral device. (This time-out event is
only functional when the clock is applied to this logical de-
vice).
When the cycle is aborted, ASTRB or DSTRB becomes in-
active, and the time-out event is signaled by asserting bit 0
of STR. If bit 4 of CTR is 1, the time-out event also pulses
the IRQ5 or IRQ7 signals when enabled. (IRQ5 and IRQ7
can be routed to any other IRQ lines via the Plug and Play
block).
EPP cycles to the external device are activated by invoking
read or write cycles to the EPP.
TABLE 4-5. Enhanced Parallel Port (EPP) Registers
Offset
00h
01h
02h
03h
04h
05h
06h
07h
Name
DTR
STR
CTR
ADDR
DATA0
DATA1
DATA2
DATA3
Description
Mode R/W
SPP Data SPP or EPP R/W
SPP Status SPP or EPP R
SPP Control SPP or EPP R/W
EPP Address
EPP R/W
EPP Data Port 0 EPP R/W
EPP Data Port 1 EPP R/W
EPP Data Port 2 EPP R/W
EPP Data Port 3 EPP R/W
4.3.2 SPP or EPP Data Register (DTR)
The DTR register is the SPP Compatible or SPP Extended
data register. A write to DTR sets the state of the eight data
pins on the 25-pin D-shell connector.
76543210
SPP or EPP Data
0 0 0 0 0 0 0 0 Reset
Register (DTR)
Offset 00h
Required
D0
D1
D2
D3
D4
D5
D6
Data Bits
D7
4.3.3 SPP or EPP Status Register (STR)
This status port is read only. A read presents the current
status of the five pins on the 25-pin D-shell connector, and
the IRQ.
76543210
SPP or EPP Status
1 1 1 1 1 1 1 1 Reset
Register (STR)
Offset 01h
Required
Time-Out Status
Reserved
IRQ Status
ERR Status
SLCT Status
PE Status
ACK Status
Printer Status
The bits of this register have the identical function in EPP
mode as in SPP mode. See Section 4.2.3 "Status Register
(STR)" on page 81 for a detailed description of each bit.
4.3.4 SPP or EPP Control Register (CTR)
This control port is read or write. A write operation to it sets
the state of four pins on the 25-pin D-shell connector, and
controls both the parallel port interrupt enable and direction.
76543210
SPP or EPP Control
1 1 0 0 0 0 0 0 Reset
Register (CTR)
Offset 02h
Required
Data Strobe Control
Automatic Line Feed Control
Printer Initialization Control
Parallel Port Input Control
Interrupt Enable
Direction Control
Reserved
Reserved
The bits of this register have the identical function in EPP
modes as in SPP modes. See Section 4.2.4 "SPP Control
Register (CTR)" on page 81 for a detailed description of
each bit.
4.3.5 EPP Address Register (ADDR)
This port is added in EPP modes to enhance system
throughput by enabling registers in the remote device to be
directly addressed by hardware.
This port can be read or written. Writing to it initiates an EPP
device or register selection operation.
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