PC87309 Datasheet, PDF (114/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Enhanced Serial Port with IR -UART2 (Logical Device 2)
TABLE 5-9. Bank Selection Encoding
BSR Bits
Bank
7 6 5 4 3 2 1 0 ^Selected
LCR
0xxxxxxx
0
10xxxxxx
1
LCR is
written
11xxxx1x
1
11xxxxx1
1
11100000
11100100
2
LCR is not
3
written
11101000
4
11101100
5
11110000
6
11110100
7
1 1 1 1 1 x 0 0 Reserved
1 1 0 x x x 0 0 Reserved
5.11.7 Modem/Mode Control Register (MCR)
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
Modem/Mode Control Register (MCR), Non-Extended
Mode
Non-Extended UART mode
76543210
Modem Control
0 0 0 0 0 0 0 0 Reset ^{Register (MCR)}
Bank 0,
000
Required
Offset 04h
DTR
RTS
RILP
ISEN or DCDLP
LOOP
Reserved
Reserved
Reserved
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to 1,
DTR is driven low. When loopback is enabled (LOOP is
set to 1), this bit internally drives DSR.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to 1,
drives RTS low. When loopback is enabled (LOOP is
set), this bit drives CTS, internally.
Bit 2 - Loopback Interrupt Request (RILP)
When loopback is enabled, this bit internally drives RI.
Otherwise it is unused.
Bit 3 - Interrupt Signal Enable (ISEN) or Loopback DCD
(DCDLP)
In normal operation (standard 16450 or 16550) mode,
this bit controls the interrupt signal and must be set to 1
in order to enable the interrupt request signal.
When loopback is enabled, the interrupt output signal is
always enabled, and this bit internally drives DCD.
New programs should always keep this bit set to 1 dur-
ing normal operation. The interrupt signal should be
controlled through the Plug-n-Play logic.
Bit 4 - Loopback Enable (LOOP)
When this bit is set to 1, it enables loopback. This bit ac-
cesses the same internal register as bit 4 of the EXCR1
register. (see “Bit 4 - Loopback Enable (LOOP)” on page
120 for more information on the Loopback mode).
0: Loopback disabled. (Default)
1: Loopback enabled.
Bits 7-5 - Reserved
Read/Write 0.
Modem/Mode Control Register (MCR), Extended Mode
In Extended mode, this register is used to select the opera-
tion mode (IrDA, Sharp, etc.) of the device and to enable the
DMA interface. In these modes, the interrupt output signal
is always enabled, and loopback can be enabled by setting
bit 4 of the EXCR1 register.
Extended Mode
76543210
Modem Control
0 0 0 0 0 0 0 0 Reset ^{Register (MCR)}
Bank 0,
Required
Offset 04h
DTR
RTS
DMA_EN
TX_DFR
Reserved
MDSL0
MDSL1
MDSL2
Bit 0 - Data Terminal Ready (DTR)
This bit controls the DTR signal output. When set to1,
DTR is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both DSR and RI.
Bit 1 - Request To Send (RTS)
This bit controls the RTS signal output. When set to1,
RTS is driven low. When loopback is enabled (LOOP is
set), this bit internally drives both CTS and DCD.
Bit 2 - DMA Enable (DMA_EN)
When set to1, DMA mode of operation is enabled. When
DMA is selected, transmit and/or receive interrupts
should be disabled to avoid spurious interrupts.
DMA cycles always address the Data Holding Registers
or FIFOs, regardless of the selected bank.
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