PC87309 Datasheet, PDF (180/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Device Specifications
10.3.10 FDC DMA Timing
Symbol Parameter
Min
Max
Unit
t_KI
DACK Inactive Pulse Width
t_KK
DACK Active Pulse Width
t_KQ
DACK Active Edge to DRQ Inactive
t_QK
DRQ to DACK Active Edge
t_QP
DRQ Period (Except Non-Burst DMA)
t_QQ
DRQ Inactive Non-Burst Pulse Width
t_QR
DRQ to RD, WR Active
t_QW
DRQ to End of RD, WR (DRQ Service Time)
t_QT
DRQ to TC Active (DRQ Service Time)
t_RQ
RD, WR Active Edge to DRQ Inactive ⁴
t_TQ
TC Active Edge to DRQ Inactive
t_TT
TC Active Pulse Width
25
65
10
8 x t_DRP1
300
15
50
nsec
nsec
65
nsec
nsec
400²
(8 x t_DRP) − (16 x t_ICP)^{1 3}
(8 x t_DRP) − (16 x t_ICP)^{1 3}
65
75
nsec
nsec
nsec
nsec
nsec
1. t_DRP and t_ICP are defined in TABLE "" on page 171.
2. Only in case of pending DRQ.
3. Values shown are with the FIFO disabled, or with FIFO enabled and THRESH = 0. For nonzero values
of THRESH, add (THRESH x 8 x t_DRP) to the values shown.
4. The active edge of RD or WR and TC is recognized only when DACK is active.
DRQ
t_QK
DACK
RD, WR
TC
t_QR
t_QT
t_QP
t_KQ
t_KK
t_QW
t_RQ
t_TQ
t_TT
t_QQ
t_KI
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