PC87309 Datasheet, PDF (143/192 Pages) National Semiconductor (TI) – PC87309 SuperI/O Plug and Play Compatible Chip in Compact 100-Pin VLJ Packaging

Enhanced Serial Port - UART1 (Logical Device 3)
Bits 2 - Number of Stop Bits (STB)
This bit specifies the number of stop bits transmitted
with each serial character.
0: One stop bit is generated. (Default)
1: If the data length is set to 5-bits via bits 1,0
(WLS1,0), 1.5 stop bits are generated. For 6, 7 or 8
bit word lengths, two stop bits are transmitted. The
receiver checks for one stop bit only, regardless of
the number of stop bits selected.
Bit 3 - Parity Enable (PEN)
This bit enable the parity bit See Table 6-7 on page 143.
The parity enable bit is used to produce an even or odd
number of 1s when the data bits and parity bit are
summed, as an error detection device.
0: No parity bit is used. (Default)
1: A parity bit is generated by the transmitter and
checked by the receiver.
Bit 4 - Even Parity Select (EPS)
When Parity is enabled (PEN is 1), this bit, together with
bit 5 (STKP), controls the parity bit as shown in Table
6-7.
0: If parity is enabled, an odd number of logic 1s are
transmitted or checked in the data word bits and
parity bit. (Default)
1: If parity is enabled, an even number of logic 1s are
transmitted or checked.
Bit 5 - Stick Parity (STKP)
When Parity is enabled (PEN is 1), this bit, together with
bit 4 (EPS), controls the parity bit as show in Table 6-7.
TABLE 6-7. Bit Settings for Parity Control
PEN
0
1
1
1
1
EPS
x
0
1
0
1
STKP
x
0
0
1
1
Selected Parity Bit
None
Odd
Even
Logic 1
Logic 0
Bit 6 - Set Break (SBRK)
This bit enables or disables a break. During the break,
the transmitter can be used as a character timer to ac-
curately establish the break duration.
This bit acts only on the transmitter front-end and has no
effect on the rest of the transmitter logic.
When set to 1 the SOUT pin is forced to a logic 0 state.
To avoid transmission of erroneous characters as a re-
sult of the break, use the following procedure to set
SBRK:
1. Wait for the transmitter to be empty. (TXEMP = 1).
2. Set SBRK to 1.
3. Wait for the transmitter to be empty, and clear SBRK
when normal transmission must be restored.
Bit 7 - Bank Select Enable (BKSE)
0: This register functions as the Line Control Register
(LCR).
1: This register functions as the Bank Select Register
(BSR).
6.5.6 Bank Selection Register (BSR)
76543210
Bank Selection
Register (BSR)
0 0 0 0 0 0 0 0 Reset
All Banks,
Offset 03h
Required
Bank Selection
BKSE-Bank Selection Enable
The Bank Selection Register (BSR) selects which register
bank is to be accessed next.
About accessing this register see the description of bit 7 of
the LCR Register.
Bits 6-0 - Bank Selection
When bit 7 is set to 1, bits 6-0 of BSR select the bank,
as shown in Table 6-8.
Bit 7 - Bank Selection Enable (BKSE)
0: Bank 0 is selected.
1: Bits 6-0 specify the selected bank.
TABLE 6-8. Bank Selection Encoding
BSR Bits
Bank
7 6 5 4 3 2 1 0 ^Selected
LCR
0xxxxxxx
10xxxxxx
11xxxx1x
11xxxxx1
11100000
11100100
0
LCR is writ-
1
ten
1
1
2
LCR is not
3
written
6.5.7 Modem/Mode Control Register (MCR)
This register controls the interface with the modem or data
communications set, and the device operational mode
when the device is in the Extended mode. The register
function differs for Extended and Non-Extended modes.
143
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