UPD70F3218 Datasheet, PDF (652/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
(2) To generate exception in service program
Service program for maskable interrupt or exception
…
…
• EIPC saved to memory or register
• EIPSW saved to memory or register
…
• TRAP instruction
…
←Acknowledges exceptions such as TRAP instruction.
• Saved value restored to EIPSW
• Saved value restored to EIPC
• RETI instruction
Priorities 0 to 7 (0 is the highest) can be set for each maskable interrupt request in multiple interrupt servicing
control by software. To set a priority level, write values to the xxICn.xxPRn0 to xxICn.xxPRn2 bits
corresponding to each maskable interrupt request. After reset, interrupt requests are masked by the
xxICn.xxMKn bit, and the priority is set to level 7 by the xxPRn0 to xxPRn2 bits.
Priorities of maskable interrupts are as follows.
(High) Level 0 > Level 1 > Level 2 > Level 3 > Level 4 > Level 5 > Level 6 > Level 7 (Low)
Interrupt servicing that has been suspended as a result of multiple interrupt servicing control is resumed after
the interrupt servicing of the higher priority has been completed and the RETI instruction has been executed.
A pending interrupt request signal is acknowledged after the current interrupt servicing has been completed
and the RETI instruction has been executed.
Caution In a non-maskable interrupt servicing routine (in the time until the RETI instruction is
executed), maskable interrupts are not acknowledged and held pending.
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User’s Manual U16889EJ1V0UD