UPD70F3218 Datasheet, PDF (537/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
In 6-byte transmission/reception (CSIMAn.ATMn bit = 0, CSIMAn.RXEAn bit = 1, CSIMAn.TXEAn bit = 1)
in automatic transmission/reception mode, buffer RAM operates as follows.
(i) When transmission/reception operation is started (refer to Figure 18-7 (a).)
When the CSITn.ATSTAn bit is set to 1, transmit data 1 (T1) is transferred from the buffer RAM to
the SIOAn register. When transmission of the first byte is completed, receive data 1 (R1) is
transferred from the SIOAn register to the buffer RAM, and the ADTCn register is incremented. Then
transmit data 2 (T2) is transferred from the buffer RAM to the SIOAn register.
(ii) 4th byte transmission/reception point (refer to Figure 18-7 (b).)
Transmission/reception of the third byte is completed, and transmit data 4 (T4) is transferred from the
buffer RAM to the SIOAn register. When transmission of the fourth byte is completed, the receive
data 4 (R4) is transferred from the SIOAn register to the buffer RAM, and the ADTCn register is
incremented.
(iii) Completion of transmission/reception (refer to Figure 18-7 (c).)
When transmission of the sixth byte is completed, receive data 6 (R6) is transferred from SIOAn
register to the buffer RAM, and the transmission/reception completion interrupt request signal
(INTCSIAn) is generated.
Figure 18-7. Buffer RAM Operation in 6-Byte Transmission/Reception
(in Automatic Transmission/Reception Mode) (1/2)
FFFFFE1FH
(a) When transmission/reception operation is started
FFFFFE05H
FFFFFE00H
Transmit data 6 (T6)
Transmit data 5 (T5)
Transmit data 4 (T4)
Transmit data 3 (T3)
Transmit data 2 (T2)
Transmit data 1 (T1)
Receive data 1 (R1) SIOAn register
5
ADTPn register
+1
0
ADTCn register
Not generated
INTCSIAn signal
Remarks 1. The above addresses are for CSIA0. For CSIA1, the addresses are FFFFFE20H to
FFFFFE3FH.
2. n = 0, 1
User’s Manual U16889EJ1V0UD
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