UPD70F3218 Datasheet, PDF (644/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
20.5 Software Exceptions
A software exception is generated when the CPU executes the TRAP instruction. Software exceptions can always
be acknowledged.
20.5.1 Operation
If a software exception occurs, the CPU performs the following processing and transfers control to a handler
routine.
<1> Saves the restored PC to EIPC.
<2> Saves the current PSW to EIPSW.
<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).
<4> Sets the PSW.EP and PSW.ID bits to 1.
<5> Loads the handler address (00000040H or 00000050H) for the software exception routine to the PC and
transfers control.
Figure 20-8 shows the software exception processing flow.
Figure 20-8. Software Exception Processing
TRAP instruction^Note
CPU processing
EIPC
EIPSW
ECR.EICC
PSW.EP
PSW.ID
PC
Restored PC
PSW
Exception code
1
1
Handler address
Exception processing
Note TRAP instruction format: TRAP vector (However, vector = 00H to 1FH)
The handler address is determined by the operand (vector) of the TRAP instruction. If the vector is 00H to 1FH,
the handler address is 00000040H, and if the vector is 10H to 1FH, the handler address is 00000050H.
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User’s Manual U16889EJ1V0UD