UPD70F3218 Datasheet, PDF (296/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
7.5.7 Pulse width measurement mode (TP0MD2 to TP0MD0 bits = 110)
In the pulse width measurement mode, 16-bit timer/event counter P starts counting when the TP0CTL0.TP0CE bit
is set to 1. Each time the valid edge input to the TIP0a pin has been detected, the count value of the 16-bit counter is
stored in the TP0CCRa register, and the 16-bit counter is cleared to 0000H.
The interval of the valid edge can be measured by reading the TP0CCRa register after a capture interrupt request
signal (INTTP0CCa) occurs.
Select either the TIP00 or TIP01 pin as the capture trigger input pin. Specify “No edge detected” by using the
TP0IOC1 register for the unused pins.
When an external clock is used as the count clock, measure the pulse width of the TIP01 pin because the external
clock is fixed to the TIP00 pin. At this time, clear the TP0IOC1.TP0IS1 and TP0IOC1.TP0IS0 bits to 00 (capture
trigger input (TIP00 pin): No edge detected).
Figure 7-34. Configuration in Pulse Width Measurement Mode
TIP00 pin
(external
event count
input/capture
trigger input)
Internal count clock
Edge
detector
Digital
noise
eliminator
Edge
detector
Count
clock
selection
TP0CE bit
TIP01 pin
(capture
trigger input)
Digital
noise
eliminator
Edge
detector
Clear
16-bit counter
TP0CCR0 register
(capture)
TP0CCR1 register
(capture)
Remark a = 0, 1
INTTP0OV signal
INTTP0CC0 signal
INTTP0CC1 signal
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User’s Manual U16889EJ1V0UD