UPD70F3218 Datasheet, PDF (477/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE (UART)
16.6.4 Receive operation
The awaiting reception state is set by setting the ASIMn.UARTEn bit to 1 and then setting the ASIMn.RXEn bit to 1.
To start the receive operation, start sampling at the falling edge when the falling of the RXDn pin is detected. If the
RXDn pin is low level at a start bit sampling point, the start bit is recognized. When the receive operation begins,
serial data is stored sequentially in the receive shift register according to the baud rate that was set. A reception
completion interrupt request signal (INTSRn) is generated each time the reception of one frame of data is completed.
Normally, the receive data is transferred from the RXBn register to memory by this interrupt servicing.
(1) Reception enabled state
The receive operation is set to the reception enabled state by setting the RXEn bit to 1.
• RXEn bit = 1: Reception enabled state
• RXEn bit = 0: Reception disabled state
In receive disabled state, the reception hardware stands by in the initial state. At this time, the contents of the
RXBn register are retained, and no reception completion interrupt or reception error interrupt is generated.
(2) Starting a receive operation
A receive operation is started by the detection of a start bit.
The RXDn pin is sampled using the serial clock from baud rate generator n (BRGn).
(3) Reception completion interrupt
When the RXEn bit = 1 and the reception of one frame of data is completed (the stop bit is detected), the
INTSRn signal is generated and the receive data within the receive shift register is transferred to the RXBn
register at the same time.
Also, if an overrun error (ASISn.OVEn bit = 1) occurs, the receive data at that time is not transferred to the
RXBn register, and either the INTSRn signal or a reception error interrupt request signal (INTSREn) is
generated according to the ASIMn.ISRMn bit setting.
Even if a parity error (ASISn.PEn bit = 1) or framing error (ASISn.FEn bit = 1) occurs during a reception
operation, the receive operation continues until stop bit is received, and after reception is completed, either
the INTSRn signal or the INTSREn signal is generated according to the ISRMn bit setting (the receive data
within the receive shift register is transferred to the RXBn register).
If the RXEn bit is cleared (0) during a receive operation, the receive operation is immediately stopped. The
contents of the RXBn register and the ASISn register at this time do not change, and the INTSRn signal or
the INTSREn signal is not generated.
The INTSRn signal or the INTSREn signal is not generated when the RXEn bit = 0 (reception is disabled).
User’s Manual U16889EJ1V0UD
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