UPD70F3218 Datasheet, PDF (530/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 18 CLOCKED SERIAL INTERFACE A (CSIA) WITH AUTOMATIC TRANSMIT/RECEIVE FUNCTION
(1) 1-byte transmission/reception communication operation
(a) 1-byte transmission/reception
When the CSIMAn.CSIAEn bit and the CSIMAn.ATEn bit = 1, 0, respectively, if transfer data is written to
the SIOAn register, the data is output via the SOA0 pin in synchronization with the SCKAn pin falling
edge, and then input via the SIAn pin in synchronization with the falling edge of the SCKAn pin, and
stored in the SIOAn register in synchronization with the rising edge 1 clock later.
Data transmission and data reception can be performed simultaneously.
If only reception is to be performed, transfer can only be started by writing a dummy value to the SIOAn
register.
When transfer of 1 byte is complete, a transmission/reception completion interrupt request signal
(INTCSIAn) is generated.
In 1-byte transmission/reception, the setting of the CSIMAn.ATMn bit is invalid.
Be sure to read data after confirming that the CSISn.TSFn bit = 0.
Caution Determine the setting procedure of alternate-function pins considering the relationship
with the communication partner.
Figure 18-2. 3-Wire Serial I/O Mode Timing
SCKAn
SIAn
1
2
3
4
5
6
7
8
DI7
DI6
DI5
DI4
DI3
DI2
DI1
DI0
SOAn
INTCSIAn
TSFn
DO7
DO6
DO5
DO4
DO3
DO2
DO1
DO0
Transfer starts at falling edge of SCKAn pin
End of transfer
SIOAn write
Caution The SOAn pin becomes low level by the SIOAn register write.
Remark n = 0, 1
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User’s Manual U16889EJ1V0UD