UPD70F3218 Datasheet, PDF (616/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 20 INTERRUPT/EXCEPTION PROCESSING FUNCTION
20.1 Overview
The V850ES/KJ1 is provided with a dedicated interrupt controller (INTC) for interrupt servicing and realize an
interrupt function that can service interrupt requests from a total of 46 to 51 sources.
An interrupt is an event that occurs independently of program execution, and an exception is an event whose
occurrence is dependent on program execution.
The V850ES/KJ1 can process interrupt requests from the on-chip peripheral hardware and external sources.
Moreover, exception processing can be started by the TRAP instruction (software exception) or by generation of an
exception event (fetching of an illegal op code) (exception trap).
20.1.1 Features
Interrupt Source
V850ES/KJ1
Interrupt
function
Non-maskable
interrupt
External
Internal
1 channel (NMI pin)
2 channels (WDT1, WDT2)
Maskable interrupt External
7 channels (all edge detection interrupts)
Internal WDT1 1 channel
TMP^{Note 1} 3 channels
TM0 12 channels
TMH 2 channels
TM5 2 channels
WT
2 channels
BRG 1 channel
UART 9 channels
CSI0 3 channels
CSIA 2 channels
IIC^{Note 2} 2 channels
KR
1 channel
AD
1 channel
Total 41 channels
Exception
function
Software exception
16 channels (TRAP00H to TRAP0FH)
16 channels (TRAP10H to TRAP1FH)
Exception trap
2 channels (ILGOP/DBG0)
Notes 1. Only in the µPD70F3218H, 70F3218HY
2. Only in products with an I²C bus (Y products)
Table 20-1 lists the interrupt/exception sources.
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User’s Manual U16889EJ1V0UD