UPD70F3218 Datasheet, PDF (285/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
Figure 7-32. Software Processing Flow in Free-Running Timer Mode (Compare Function) (2/2)
<1> Count operation start flow
START
Register initial setting
TP0CTL0 register
(TP0CKS0 to TP0CKS2 bits)
TP0CTL1 register,
TP0IOC0 register,
TP0IOC2 register,
TP0OPT0 register,
TP0CCR0 register,
TP0CCR1 register
Initial setting of these registers
is performed before setting the
TP0CE bit to 1.
TP0CE bit = 1
The TP0CKS0 to TP0CKS2 bits
can be set at the same time
when counting has been started
(TP0CE bit = 1).
<2> Overflow flag clear flow
Read TP0OPT0 register
(check overflow flag).
NO
TP0OVF bit = 1
YES
Execute instruction to clear
TP0OVF bit (CLR TP0OVF).
<3> Count operation stop flow
TP0CE bit = 0
Counter is initialized and
counting is stopped by
clearing TP0CE bit to 0.
STOP
User’s Manual U16889EJ1V0UD
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