UPD70F3218 Datasheet, PDF (311/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 8 16-BIT TIMER/EVENT COUNTER 0
Cautions 1. If 0000H is set to the CR0n1 register, an interrupt request signal (INTTM0n1) is
generated after overflow of the TM0n register, after clear & start on a match between
the TM0n register and CR0n0 register, after clear by the valid edge of the TI0n0 pin,
or after clear by a one-shot pulse output trigger.
2. When the P33, P35, P613, P92, and P94 pins are used as the valid edges of TI000,
TI010, TI020, TI030, and TI051, they cannot be used as timer outputs (TO00 to TO03,
TO05). Moreover, when used as TO00 to TO03 and TO05, these pins cannot be used
as the valid edges of TI000, TI010, TI020, TI030, and TI051.
3. If, when the CR0n1 register is used as a capture register, the register read interval
and capture trigger input conflict, the read data becomes undefined (but the capture
data itself is normal). Moreover, when the count stop input and capture trigger input
conflict, the capture data becomes undefined.
4. The CR0n1 register can be rewritten during TM0n register operation only in the PPG
output mode. Refer to 8.4.2 PPG output operation.
User’s Manual U16889EJ1V0UD
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