UPD70F3218 Datasheet, PDF (293/884 Pages) NEC – 32-Bit Single-Chip Microcontrollers

CHAPTER 7 16-BIT TIMER/EVENT COUNTER P (TMP)
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an
overflow may occur more than once from the first capture trigger to the next. First, an example of incorrect
processing is shown below.
Example of incorrect processing when capture trigger interval is long
FFFFH
Da0
16-bit counter
Da1
0000H
TP0CE bit
TIP0a pin input
TP0CCRa register
Da0
Da1
INTTP0OV signal
TP0OVF bit
1 cycle of 16-bit counter
<1> <2>
Pulse width
<3> <4>
The following problem may occur when long pulse width is measured in the free-running timer mode.
<1> Read the TP0CCRa register (setting of the default value of the TIP0a pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TP0CCRa register.
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + Da1 − Da0)
(incorrect).
Actually, the pulse width must be (20000H + Da1 − Da0) because an overflow occurs twice.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may
not be obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or
use software. An example of how to use software is shown next.
User’s Manual U16889EJ1V0UD
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