MC68HC912B32 Datasheet, PDF (95/128 Pages) Motorola, Inc – 16-Bit Microcontroller

Pin Mode
SPC0¹
MSTR
MISO²
MOSI³
#1
Normal
0
#2
0
Slave Out Slave In
1
Master In Master Out
#3
Bidirectional
1
#4
0
Slave I/O GPI/O
1
GPI/O Master I/O
NOTES:
1. The serial pin control 0 bit enables bidirectional configurations.
2. Slave output is enabled if DDS4 = 1, SS = 0 and MSTR = 0. (#1, #3)
3. Master output is enabled if DDS5 = 1 and MSTR = 1. (#2, #4)
4. SCK output is enabled if DDS6 = 1 and MSTR = 1. (#2, #4)
5. SS output is enabled if DDS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)
SCK⁴
SCK In
SCK Out
SCK In
SCK Out
SS⁵
SS In
SS I/O
SS In
SS I/O
SP0BR — SPI Baud Rate Register
$00D2
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
SPR2 SPR1 SPR0
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write anytime.
At reset, E Clock divided by 2 is selected.
SPR[2:0] — SPI Clock (SCK) Rate Select Bits
These bits are used to specify the SPI clock rate.
Table 31 SPI Clock Rate Selection
SPR2 SPR1 SPR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
E Clock
Divisor
2
4
8
16
32
64
128
256
Frequency at Frequency at
E Clock = 4 MHz E Clock = 8 MHz
2.0 MHz
4.0 MHz
1.0 MHz
2.0 MHz
500 kHz
1.0 MHz
250 kHz
500 kHz
125 kHz
250 kHz
62.5 kHz
125 kHz
31.3 kHz
62.5 kHz
15.6 kHz
31.3 kHz
SP0SR — SPI Status Register
$00D3
Bit 7
6
5
4
3
2
1
Bit 0
SPIF
WCOL
0
MODF
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Read anytime. Write has no meaning or effect.
SPIF — SPI Interrupt Request
SPIF is set after the eighth SCK cycle in a data transfer and it is cleared by reading the SP0SR register
(with SPIF set) followed by an access (read or write) to the SPI data register.
WCOL — Write Collision Status Flag
The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated
because the error status flag can be read upon completion of the transfer that was in progress at the
time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
95