MC68HC912B32 Datasheet, PDF (79/128 Pages) Motorola, Inc – 16-Bit Microcontroller

TC3 — Timer Input Capture/Output Compare Register 3
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC4 — Timer Input Capture/Output Compare Register 4
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC5 — Timer Input Capture/Output Compare Register 5
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC6 — Timer Input Capture/Output Compare Register 6
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC7 — Timer Input Capture/Output Compare Register 7
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
$0096–$0097
1
Bit 0
9
Bit 8
1
Bit 0
$0098–$0099
1
Bit 0
9
Bit 8
1
Bit 0
$009A–$009B
1
Bit 0
9
Bit 8
1
Bit 0
$009C–$009D
1
Bit 0
9
Bit 8
1
Bit 0
$009E–$009F
1
Bit 0
9
Bit 8
1
Bit 0
Depending on the TIOS bit for the corresponding channel, these registers are used to latch the value
of the free-running counter when a defined transition is sensed by the corresponding input capture edge
detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to these registers have no meaning
or effect during input capture. All timer input capture/output compare registers are reset to $0000.
PACTL — Pulse Accumulator Control Register
$00A0
Bit 7
6
5
4
3
2
1
Bit 0
0
PAEN PAMOD PEDGE CLK1
CLK0 PAOVI
PAI
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator system disabled
1 = Pulse accumulator system enabled
PAEN is independent from TEN.
PAMOD — Pulse Accumulator Mode
0 = Event counter mode
1 = Gated time accumulation mode
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
79