MC68HC912B32 Datasheet, PDF (75/128 Pages) Motorola, Inc – 16-Bit Microcontroller

When the OC7Mn bit is set, a successful OC7 action will override a successful OC[6:0] compare action
during the same cycle; therefore, the OCn action taken will depend on the corresponding OC7D bit.
TCNT — Timer Count Register
$0084–$0085
Bit 7
6
5
4
3
2
1
Bit 0
Bit 15
14
13
12
11
10
9
Bit 8
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
Read anytime.
Write has no meaning or effect in the normal mode; only writable in special modes (SMODN = 0).
The period of the first count after a write to the TCNT registers may be a different size because the write
is not synchronized with the prescaler clock.
TSCR — Timer System Control Register
$0086
Bit 7
6
5
4
3
2
1
Bit 0
TEN
TSWAI TSBCK TFFCA
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
Read or write anytime.
TEN — Timer Enable
0 = Disables the timer, including the counter. Can be used for reducing power consumption.
1 = Allows the timer to function normally.
If for any reason the timer is not active, there is no ÷64 clock for the pulse accumulator since the E÷64
is generated by the timer prescaler.
TSWAI — Timer Stops While in Wait
0 = Allows the timer to continue running during wait.
1 = Disables the timer when the MCU is in the wait mode. Timer interrupts cannot be used to get
the MCU out of wait.
TSBCK — Timer Stops While in Background Mode
0 = Allows the timer to continue running while in background mode.
1 = Disables the timer whenever the MCU is in background mode. This is useful for emulation.
TFFCA — Timer Fast Flag Clear All
0 = Allows the timer flag clearing to function normally.
1 = For TFLG1($8E), a read from an input capture or a write to the output compare channel ($90–
$9F) causes the corresponding channel flag, CnF, to be cleared. For TFLG2 ($8F), any access
to the TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register ($A2,
$A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1). This has the advantage of
eliminating software overhead in a separate clear sequence. Extra care is required to avoid ac-
cidental flag clearing due to unintended accesses.
TQCR — Reserved
$0087
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
75