MC68HC912B32 Datasheet, PDF (60/128 Pages) Motorola, Inc – 16-Bit Microcontroller

CR2
0
0
0
0
1
1
1
1
CR1
0
0
1
1
0
0
1
1
Table 21 COP Watchdog Rates (RTBYP = 0)
CR0 Divide E By:
0
OFF
1
2¹³
0
2¹⁵
1
2¹⁷
0
2¹⁹
1
2²¹
0
2²²
1
2²³
At E = 4.0 MHz
Time-Out
–0 to +2.048 ms
OFF
2.048 ms
8.1920 ms
32.768 ms
131.072 ms
524.288 ms
1.048 s
2.097 s
At E = 8.0 MHz
Time-Out
–0 to +1.024 ms
OFF
1.024 ms
4.096 ms
16.384 ms
65.536 ms
262.144 ms
524.288 ms
1.048576 s
COPRST — Arm/Reset COP Timer Register
$0017
Bit 7
6
5
4
3
2
1
Bit 0
Bit 7
6
5
4
3
2
1
Bit 0
RESET:
0
0
0
0
0
0
0
0
Always reads $00.
Writing $55 to this address is the first step of the COP watchdog sequence.
Writing $AA to this address is the second step of the COP watchdog sequence. Other instructions may
be executed between these writes but both must be completed in the correct order prior to time-out to
avoid a watchdog reset. Writing anything other than $55 or $AA causes a COP reset to occur.
10.6 Clock Divider Chains
Figure 11, Figure 12, Figure 13, and Figure 14 summarize the clock divider chains for the various pe-
ripherals on the MC68HC912B32.
EXTAL
XTAL
OSCILLATOR
AND
CLOCK
GENERATOR
SYSCLK
÷2
T CLOCK ^TCLKs
GENERATOR
TO CPU
E AND P CLOCK
GENERATOR
ECLK
PCLK
TO BDM,
BUSES, SPI,
ATD, SCI, TIM,
PULSE ACC,
RTI, COP,
PWM, BDLC
Figure 11 Clock Divider Chain
HC912B32 CLOCK DIV CHAIN
MOTOROLA
60
MC68HC912B32
MC68HC912B32TS/D