MC68HC912B32 Datasheet, PDF (117/128 Pages) Motorola, Inc – 16-Bit Microcontroller

E CLOCK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
OF BIT TIME
SYNCHRONIZATION
UNCERTAINTY
TARGET SENSES BIT
9 CYCLES
Figure 27 BDM Host to Target Serial Bit Timing
EARLIEST
START OF
NEXT BIT
HC12A4 BDM HOST TO TARGET TIM
E CLOCK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED
START OF BIT
TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 28 BDM Target to Host Serial Bit Timing (Logic 1)
EARLIEST
START OF
NEXT BIT
HC12A4 BDM TARGET TO HOST TIM 1
Figure 28 shows the host receiving a logic one from the target MC68HC912B32 MCU. Since the host
is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge
on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long
enough for the target to recognize it (at least two target E cycles). The host must release the low drive
before the target MCU drives a brief active-high speed-up pulse seven cycles after the perceived start
of the bit time. The host should sample the bit level about ten cycles after it started the bit time.
MC68HC912B32
MC68HC912B32TS/D
MOTOROLA
117