SDA9400 Datasheet, PDF (89/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
9 Characteristics (Assuming Recommended Operating Conditions)
Parameter
Symbol Min Max Unit Remark
Average Supply Current
t.b.d. t.b.d. mA
All Digital Inputs (Including I/O Inputs)
All V_DD pins, typ. t.b.d.mA
Input Capacitance
10
pF
Input Leakage Current
-5
5
µA
TTL Inputs: YIN, UVIN, HIN, VIN (Referenced To CLK1)
Set-Up Time
t_SU
7
ns
Input Hold Time
t_IH
6
ns
TTL Inputs: HEXT, VEXT (Referenced To X1/CLK2)
see diagr. 11.3
Set-Up Time
t_SU
7
ns
see diagr. 11.3
Input Hold Time
t_IH
6
ns
TTL Outputs: YOUT, UVOUT, HREF, INTERLACED (Referenced To CLKOUT*)
Hold time
t_OH
6
ns
Delay time
t_OD
25
ns
TTL Outputs: HOUT, VOUT (Referenced To CLKOUT)
see diagr. 11.3
CL = 30 pF, 27 MHz
Hold time
t_OH
6
ns
see diagr. 11.3
Delay time
t_OD
25
ns
CL = 50 pF, 27 MHz
TTL Outputs: YOUT, UVOUT, HREF, INTERLACED (Referenced To CLKOUT)
Hold time
t_OH
3
ns
Delay time
t_OD
15
ns
TTL Outputs: HOUT, VOUT (Referenced To CLKOUT)
see diagr. 11.3
CL = 30 pF, 40,5 MHz
Hold time
t_OH
3
Delay time
t_OD
15
TTL Inputs: SYNCEN (Referenced To CLK1)
ns
see diagr. 11.3
ns
CL = 50 pF, 40,5 MHz
Set-Up Time
Input Hold Time
t_SU2
25
t_IH2
0
ns
see diagr. 11.3
ns
*: see also Clock concept on page 37
Micronas
89
Preliminary Data Sheet