SDA9400 Datasheet, PDF (60/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
4:2:2. The representation of the samples of the chrominance signal is programmable as positive
dual code (unsigned, parameter TWOOUT=0) or two's complement code (TWOOUT=1, see also
I²C bus format on page 64, I²C bus parameter 17h).
Output data format
Data
Pin
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
UVOUT7
UVOUT6
UVOUT5
UVOUT4
UVOUT3
UVOUT2
UVOUT1
UVOUT0
4:2:2 Parallel
Y₀₇
Y₁₇
Y₀₆
Y₁₆
Y₀₅
Y₁₅
Y₀₄
Y₁₄
Y₀₃
Y₁₃
Y₀₂
Y₁₂
Y₀₁
Y₁₁
Y₀₀
Y₁₀
U₀₇
V₀₇
U₀₆
V₀₆
U₀₅
V₀₅
U₀₄
V₀₄
U₀₃
V₀₃
U₀₂
V₀₂
U₀₁
V₀₁
U₀₀
V₀₀
X ab: X: signal component a: sample number b: bit number
6.7 High data rate processing (HDR)
The output signal can be vertically expanded. The expansion as well as the different scan rate
conversion algorithms are processed in the HDR block. For the vertical expansion line memories
are used. If the operation frequency X1/CLK2 is higher than 27 MHz plus 10%, the line memories
will not work correctly any more. In this case only simple processing will be possible. Simple
processing means, that the vertical expansion must be disabled. To force simple processing the
parameter FREQR is used. Furthermore all static operation modes are disabled, which needs the
interpolation into another raster position like Micronas soft mix mode.
Output write parameter: FREQR
FREQR
0
X1/CLK2
<= 27 MHZ + 10%
Vertical expansion
depends on VERINT
Micronas
60
Preliminary Data Sheet