SDA9400 Datasheet, PDF (17/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
output delay time for YIN, UVIN, HIN and VIN (e.g. Micronas VPC32XX, output delay: 35 ns). For
this application the half system clock CLK1 (13.5 MHz) from the front-end should be provided at this
pin. In case the front-end is working at 27.0 MHz with sync signals having delay times smaller than
25 ns, this input can be set to low level (SYNCEN=V_SS) (e.g. Micronas SDA 9206, output delay: 25
ns). Thus the signals YIN, UVIN, HIN and VIN are sampled with the CLK1 system clock when the
SYNCEN input is low.
SYNCEN signal
CLK1
SYNCEN
YIN
x
UVIN
x
y0
y1
y2
y3
u0
v0
u2
v2
YINen
x
y0
y1
y2
y3
UVINen
x
u0
v0
u2
v2
HIN/VIN
HINen/VINen
The figure below shows the input timing and the functionality of the NAPIPDL and NAPIPPH
parameter in case of CCIR 656 and 4:2:2 parallel data input format for one example. The signals
HINint, YINint and UVint are the internal available sampled input signals.
Input timing
CLK1
HIN
HINint
CCIR 656 interface
YIN
YINint
UVINint
xxx
u0 y0 v0 y1 u2 y2 v2 y3 u4 y4
(NAPIPDL* 4 + NAPIPPH + 7) * Tclk1
=(0 * 4 + 2 + 7) * Tclk1 = 9 Tclk1 (e.g.)
(NAPIPDL* 4 + NAPIPPH + 7) * Tclk1
=(0 * 4 + 3 + 7) * Tclk1 = 10 Tclk1 (e.g.)
u0
v0
u2
v2
u4
y0
y1
y2
y3
u0
v0
u2
v2
4:2:2 interface
YIN
xxx
UVIN
xxx
y0
y1
y2
y3
y4
u0
v0
u2
v2
u4
YINint
UVINint
y0
y1
y3
y4
u0
v0
u2
v2
Micronas
17
Preliminary Data Sheet