SDA9400 Datasheet, PDF (43/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
UBORDER and VBORDER. To avoid transition artifacts of digital filters the number of active pixels
per line (parameter APPL) can be symmetrically reduced using the CAPP parameter. The figure
below shows also the internal signal ALOP, which marks the active pixels of the line.
Timing diagram of output signals
X1/CLK2
HOUT
64 * Tx1/clk2
YOUT
PPLOP * 2 Tx1/clk2
e.g. 432 * 2 / 27 MHz = 32 µs
x
y0 y1 y2 y3 y4 y5
UVOUT
x
u0 v0 u2 v2 u4 v4
((HOUTDEL + 1) * 4 + PD)* Tx1/clk2
HREF
YOUT
UVOUT
APPLOP * 16 * Tx1/clk2
e.g. 45 * 16 = 720 Tx1/clk2
x
YB YB YB YB y0 y1
x
UB VB UB VB u0 v4
((HOUTDEL + 1 + NAPOP) * 4 + PD)* Tx1/clk2
ALOP
ym-2 ym-1
um-2 vm-´2
YB YB
UB VB
x
x
m=APPL*16
x
x
m=APPL*16
Output write parameter
Parameter
HOUTFR
1: freerun
0: locked
mode
EXSYN
1: on
0: off
YBORDER
UBORDER
VBORDER
CAPP
00: k = 0
01: k = 8
10: k = 16
11: k = 24
Subaddress
Description
14h
HOUT generator mode select
14h
External synchronization select
17h
Y border value (four MSB of the 8 bit colour)
18h
U border value (four MSB of the 8 bit colour)
18h
V border value (four MSB of the 8 bit colour)
10h
Reducing factor for the Active Pixels Per Line Value
(APPL)
Number of active pixels per line = 16 * APPL - 2*k
Micronas
43
Preliminary Data Sheet