SDA9400 Datasheet, PDF (16/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
Input sync formats
FORMAT
00
01 (CCIR 656 only
data)
10
11 (full CCIR 656)
HIN
PAL/NTSC
PAL/NTSC
CCIR 656
x
VIN
PAL/NTSC
PAL/NTSC
CCIR 656
x
YIN
4:2:2
CCIR 656
CCIR 656
CCIR 656
UVIN
4:2:2
x
x
x
The amplitude resolution for each input signal component is 8 bit, the maximum clock frequency is
27 MHz. Consequently the SDA 9400 is dedicated for application in high quality digital video
systems.
The figure below shows the generation of the internal H- and V-syncs in case of full CCIR 656
mode. The H656 sync is generated after the EAV. The V656 and F656 signals change
synchronously with the EAV timing reference code.
Explanation of 656 format
CLK1 (27 MHz)
CCIR 656 interface
YIN
EAV
SAV
u0 y0 v0 y1 u2 y3
EAV
288 Tclk1(PAL)
276 Tclk1(NTSC)
1728 Tclk1(PAL)
1716 Tclk1(NTSC)
CLK1 (27 MHz)
YIN
x
EAV
x
x
SAV
x
x
EAV
x
H656
V656
(e.g.)
F656
(e.g.)
11111111
MSB
LSB
11111111
EAV
00000000
00000000
SAV
00000000
00000000
1FV1P₃P₂P₁P₀
1FV0P₃P₂P₁P₀
F = 0 during field 1(A)
F = 1 during field 2(B)
V = 0 elsewhere
V = 1 during field blanking
The figure below explains the functionality of the SYNCEN signal. The SDA 9400 needs the
SYNCEN (synchronization enable) signal, which is used to gate the YIN, UVIN as well as the HIN
and the VIN signal. This is implemented for front-ends which are working with 13.5 MHz and a large
Micronas
16
Preliminary Data Sheet