SDA9400 Datasheet, PDF (7/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
3 Block diagram
HIN
VIN
SYNCEN
ISC
Input sync
controller
YIN
UVIN
RESET
IFC
Input
format
conversion
I²C
I²C Bus
Interface
SDA SCL
LDR
Vertical,
Horizontal
decimation
Noise reduction
and measurement
Motion detector
Movie mode
and phase
detection
LM
Line memory
MC
Memory Controller
ED
eDRAM
Interfaces
Data buffer
Voltage control
Test controller
PLL1
Clock doubling
CLK1
OSC
Output sync
controller
VOUT/VEXT
HOUT/HEXT
HREF
INTERLACED
HDR
Scan rate
conversion
Vertical
interpolation
OFC
output
format
conversion
YOUT
UVOUT
CLKOUT
LM
Line memory
PLL2
Clock
doubling
X1/CLK2
X2
The SDA 9400 contains the blocks, which will be briefly described below:
ISC - Flexible input sync controller
IFC - Input format conversion
LDR - Low data rate processing (noise reduction and measurement, vertical compression,
horizontal compression, motion detector for scan rate conversion, movie mode and phase detector)
MC - Memory controller
OSC - Flexible output sync controller
OFC - Output format conversion
HDR - High data rate processing (scan rate conversion, vertical expansion)
I²C - I²C bus interface
PLL1/2 - PLL for frequency doubling
LM - Line memory core
ED - eDRAM core
Micronas
7
Preliminary Data Sheet