SDA9400 Datasheet, PDF (42/94 Pages) Micronas – Scan Rate Converter using Embedded DRAM Technology Units

SDA 9400
Parameter
[Default value]
NAPOP
[0]
APPLOP
[45]
APPL
PPLOP
[432]
Subaddress
0Eh
10h
internal
11h, 12h
Description
Not Active Pixel OutPut defines the number of not active
pixels (e.g. coloured border values)
Active Pixels Per Line OutPut defines the number of
pixels per line including border pixels
Active Pixels Per Line defines the number of active
pixels (see also Horizontal compression on page 19,
APPLIP)
Pixel Per Line OutPut defines the number of pixels bet-
ween two consecutive H-Syncs (only valid for
HOUTFR=1)
The next paragraphs describe the HOUT and VOUT generator in more detail. Both generators have
a so called “locked-mode” and “freerunning-mode”. Not all combinations of the modi make sense.
The table below shows ingenious configurations.
Ingenious configurations of the HOUT and VOUT generator
Mode
“H-and-V-locked”
“H-freerunning-V-locked”
“H-and-V-freerunning”
External synchronization
EXSYN
0
0
0
1
HOUTFR
0
1
1
0
VOUTFR
0
0
1
0
CLK11EN
1
1
1
1
CLK21EN
1
0
0
0
FREQR
0
0
0 or 1
0 or 1
CONV
by I²C-bus
by I²C-bus
0
0
6.5.1 HOUT generator
The HOUT generator has two operation modes, which can be selected by the parameter HOUTFR.
The HOUT signal is active high (HOUTPOL=0) for 64 clock cycles (X1/CLK2). In the freerunning-
mode the HOUT signal is generated depending on the PPLOP parameter. In the locked-mode the
HOUT signal is locked on the incoming H-Sync signal HIN. In case of external synchronization
(EXSYN=1), no HOUT signal is generated. The SDA 9400 needs in this case an external H-Sync
(HEXT). The polarity of the HEXT signal as well as of the HOUT signal is programmable by the
parameter HOUTPOL. In case of external synchronization the HOUT generator has to be set into
the locked-mode (see also Output sync controller (OSC) on page 40).
The HREF signal marks the active part of a line. The figure below shows the timing relation of the
HOUT and the HREF signal. The distance is programmable by the parameter HOUTDEL. PD
means processing delay of the internal data processing (PD=36 X1/CLK2 clocks). The length of the
active part is determined by the parameter APPLOP. If the number of the active pixels (internal
parameter APPL, see also Horizontal compression on page 19) is smaller than the number of the
displayed pixels (e.g. displaying a 4:3 source on a 16:9 screen), a coloured border can be defined
using the NAPOP parameter. The border colour is defined by the parameters YBORDER,
Micronas
42
Preliminary Data Sheet