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| MT40A512M8RH-083E Datasheet, PDF (93/365 Pages) Micron Technology – Programmable data strobe preambles | |||
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4Gb: x4, x8, x16 DDR4 SDRAM
Multipurpose Register
Table 34: MPR Readout Staggered Format, x4 â Consecutive READs (Continued)
Stagger
DQ2
DQ3
UI[7:0]
MPR2
MPR3
UI[15:8]
MPR3
MPR0
UI[23:16]
MPR0
MPR1
UI[31:24]
MPR1
MPR2
UI[39:32]
MPR2
MPR3
UI[47:40]
MPR3
MPR0
UI[55:48]
MPR0
MPR1
UI[63:56]
MPR1
MPR2
For the x8 configuration, the same pattern is repeated on the lower nibble as on the up-
per nibble. READs to other MPR data pattern locations follow the same format as the x4
case. A read example to MPR0 for x8 and x16 configurations is shown below.
Table 35: MPR Readout Staggered Format, x8 and x16
x8 READ MPR0 Command
Stagger
UI[7:0]
DQ0
MPR0
DQ1
MPR1
DQ2
MPR2
DQ3
MPR3
DQ4
MPR0
DQ5
MPR1
DQ6
MPR2
DQ7
MPR3
x16 READ MPR0 Command
Stagger
UI[7:0]
DQ0
MPR0
DQ1
MPR1
DQ2
MPR2
DQ3
MPR3
DQ4
MPR0
DQ5
MPR1
DQ6
MPR2
DQ7
MPR3
x16 READ MPR0 Command
Stagger
UI[7:0]
DQ8
MPR0
DQ9
MPR1
DQ10
MPR2
DQ11
MPR3
DQ12
MPR0
DQ13
MPR1
DQ14
MPR2
DQ15
MPR3
MPR READ Waveforms
The following waveforms show MPR read accesses.
Figure 33: MPR READ Timing
CK_c
CK_t
Command
Address
T0
Ta0
Ta1
MPE Enable
PREA
MRS1
DES
tRP
tMOD
Valid
Valid
Valid
Tb0
READ
Add2
Tc0
DES
Valid
Tc1
DES
Valid
Tc2
DES
Valid
Tc3
DES
Valid
Td0
DES
Valid
Td1
Te0
Tf0
Tf1
MPE Disable
DES
MRS3
Valid4
tMPRR
tMOD
Valid
Valid
Valid
DES
Valid
CKE
DQS_t,
DQS_c
DQ
PL5 + AL + CL
UI0 UI1 UI2 UI5 UI6 UI7
Time Break
Notes: 1. tCCD_S = 4tCK, Read Preamble = 1tCK.
2. Address setting:
A[1:0] = 00b (data burst order is fixed starting at nibble, always 00b here)
Donât Care
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
93
Micron Technology, Inc. reserves the right to change products or specifications without notice.
 2014 Micron Technology, Inc. All rights reserved.
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