MT40A512M8RH-083E Datasheet, PDF (362/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Electrical Characteristics and AC Timing Parameters: 2666
Through 3200
Notes:
1. Maximum limit not applicable.
2. ^tCCD_L and ^tDLLK should be programmed according to the value defined per operating
frequency.
3. Data rate is greater than or equal to 1066 Mb/s.
4. RFU.
5. WRITE-to-READ when CRC and DM are both not enabled.
6. WRITE-to-READ delay when CRC and DM are both enabled.
7. The start of internal write transactions is defined as follows:
• For BL8 (fixed by MRS and on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (on-the-fly): rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): rising clock edge two clock cycles after WL
8. For these parameters, the device supports ^tnPARAM [nCK] = RU{^tPARAM [ns]/^tCK (AVG)
[ns]}, in clock cycles, assuming all input clock jitter specifications are satisfied.
9. Although unlimited row accesses to the same row is allowed within the refresh period,
excessive row accesses to the same row over a long term can result in degraded opera-
tion.
10. When operating in 1^tCK WRITE preamble mode.
11. When operating in 2^tCK WRITE preamble mode.
12. When CA parity mode is selected and the DLLoff mode is used, each REF command re-
quires an additional "PL" added to ^tRFC refresh time.
13. DRAM devices should be evenly addressed when being accessed. Disproportionate ac-
cesses to a particular row address may result in reduction of the product lifetime and/or
reduction in data retention ability.
14. Applicable from ^tCK (AVG) MIN to ^tCK (AVG) MAX as stated in the Speed Bin tables.
15. JEDEC specifies a minimum of five clocks.
16. The maximum read postamble is bound by ^tDQSCK (MIN) plus ^tQSH (MIN) on the left
side and ^tHZ(DQS) MAX on the right side.
17. The reference level of DQ output signal is specified with a midpoint as a widest part of
output signal eye, which should be approximately 0.7 × V_DDQ as a center level of the
static single-ended output peak-to-peak swing with a driver impedance of 34 ohms and
an effective test load of 50 ohms to V_TT = V_DDQ.
18. JEDEC hasn't agreed upon the definition of the deterministic jitter; the user should fo-
cus on meeting the total limit.
19. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of ^tCK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below ^tCK (AVG) MIN.
20. The actual ^tCAL minimum is the larger of 3 clocks or 3.748ns/^tCK; the table lists the ap-
plicable clocks required at targeted speed bin.
21. The maximum READ preamble is bounded by ^tLZ(DQS) MIN on the left side and ^tDQSCK
(MAX) on the right side. See figure in Clock to Data Strobe Relationship. Boundary of
DQS Low-Z occur one cycle earlier in 2^tCK toggle mode which is illustrated in READ Pre-
amble.
22. DQ falling signal middle-point of transferring from HIGH to LOW to first rising edge of
DQS differential signal cross-point.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
362
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