MT40A512M8RH-083E Datasheet, PDF (313/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Current Specifications – Measurement Conditions
Table 136: Basic I_DD, I_PP, and I_DDQ Measurement Conditions (Continued)
Symbol
I_DD2NT
I_DDQ2NT
I_DD2P
I_DD2Q
I_DD3N
I_PPSB
I_DD3P
I_DD4R
I_DD4W
Description
Precharge Standby ODT Current
CKE: HIGH; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: stable at 1; Command, ad-
dress, bank gropup address, bank address inputs: partially toggling according to the I_DD2NT and I_DDQ2NT Meas-
urement-Loop Pattern table; Data I/O: V_SSQ; DM_n: stable at 1; Bank activity: all banks closed; Output buffer
and R_TT: enabled in mode registers;² ODT signal: toggling according to the I_DD2NT and I_DDQ2NT Measurement-
Loop Pattern table; Pattern details: see the I_DD2NT and I_DDQ2NT Measurement-Loop Pattern table
Precharge Standby ODT I_DDQ Current
Has the same definition as I_DD2NT above, with the exception of measuring I_DDQ current instead of I_DD current
Precharge Power-Down Current
CKE: LOW; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: stable at 0; Data I/O: V_DDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and R_TT: Enabled in mode registers;² ODT signal: stable at 0
Precharge Quiet Standby Current
CKE: HIGH; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: stable at 0; Data I/O: V_DDQ; DM_n: stable at 1; Bank activity: all
banks closed; Output buffer and R_TT: Enabled in mode registers;² ODT signal: stable at 0
Active Standby Current (AL = 0)
CKE: HIGH; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: partially toggling according to the I_DD2N and I_DD3N Measure-
ment-Loop Pattern table; Data I/O: V_DDQ; DM_n: stable at 1; Bank activity: all banks open; Output buffer and
R_TT: Enabled in mode registers;² ODT signal: stable at 0; Pattern details: see the I_DD2N and I_DD3N Measurement-
Loop Pattern table
Active Standby I_PPSB Current (AL = 0)
Same conditions as I_DD3N above
Active Power-Down Current (AL = 0)
CKE: LOW; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: stable at 1; Command, ad-
dress, bank group address, bank address inputs: stable at 1; Data I/O: V_DDQ; DM_n: stable at 1; Bank activity: all
banks open; Output buffer and R_TT: Enabled in mode registers;² ODT signal: stable at 0
Operating Burst Read Current (AL = 0)
CKE: HIGH; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹⁵ AL: 0; CS_n: HIGH between RD; Com-
mand, address, bank group address, bank address inputs: partially toggling according to the I_DD4R Measure-
ment-Loop Pattern table; Data I/O: seamless read data burst with different data between one burst and the
next one according to the I_DD4R Measurement-Loop Pattern table; DM_n: stable at 1; Bank activity: all banks
open, RD commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see the I_DD4R Measurement-Loop Pattern table);
Output buffer and R_TT: Enabled in mode registers;² ODT signal: stable at 0; Pattern details: see the I_DD4R Meas-
urement-Loop Pattern table
Operating Burst Write Current (AL = 0)
CKE: HIGH; External clock: on; ^tCK, CL: see the previous table; BL: 8;¹ AL: 0; CS_n: HIGH between WR; Com-
mand, address, bank group address, bank address inputs: partially toggling according to the I_DD4W Measure-
ment-Loop Pattern table; Data I/O: seamless write data burst with different data between one burst and the
next one according to the I_DD4W Measurement-Loop Pattern table; DM: stable at 0; Bank activity: all banks
open, WR commands cycling through banks: 0, 0, 1, 1, 2, 2, ... (see I_DD4W Measurement-Loop Pattern table);
Output buffer and R_TT: enabled in mode registers (see note2); ODT signal: stable at HIGH; Pattern details: see
the I_DD4W Measurement-Loop Pattern table
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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