MT40A512M8RH-083E Datasheet, PDF (229/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
WRITE Operation
Figure 173: Nonconsecutive WRITE (BL8) with 1^tCK Preamble in Same or Different Bank Group
T0
T1
T2
T3
T4
T5
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
DES
t_{CCD_S/L = 5}
WL = AL + CWL = 9
DES
WRITE
DES
DES
DES
DES
DES
DES
BGa
or BGb
Bank
Col b
t_WPRE
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = AL + CWL = 9
DES
DES
DES
DES
DES
DES
t_WR
4 Clocks
t_WTR
t_WPST
DI DI DI DI DI DI DI DI
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, AL = 0, CWL = 9, Preamble = 1^tCK, ^tCCD_S/L = 5^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T5.
5. CA parity = Disable, CS to CA latency = Disable, Write DBI = Disable, Write CRC = Disable.
6. The write recovery time (^tWR) and write timing parameter (^tWTR) are referenced from
the first rising clock edge after the last write data shown at T18.
Figure 174: Nonconsecutive WRITE (BL8) with 2^tCK Preamble in Same or Different Bank Group
T0
T1
T2
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
CK_c
CK_t
Command WRITE
Bank Group
BGa
Address
Address
Bank
Col n
DQS_t,
DQS_c
DQ
DES
DES
WRITE
DES
t_{CCD_S/L = 6}
BGa
or BGb
Bank
Col b
WL = AL + CWL = 10
DES
DES
DES
DES
DES
DES
DES
DES
t_WPRE
t_WPRE
DI DI DI DI DI DI DI DI
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
WL = AL + CWL = 10
DES
DES
DES
DES
DES
t_WR
4 Clocks
t_WTR
t_WPST
DI DI DI DI DI DI DI DI
b b+1 b+2 b+3 b+4 b+5 b+6 b+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, AL = 0, CWL = 9 + 1 = 10 (see Note 8), Preamble = 2^tCK, ^tCCD_S/L = 6^tCK.
2. DI n (or b) = data-in from column n (or column b).
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during
WRITE commands at T0 and T6.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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