MT40A512M8RH-083E Datasheet, PDF (34/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Functional Description
Functional Description
The DDR4 SDRAM is a high-speed dynamic random-access memory internally config-
ured as sixteen banks (4 bank groups with 4 banks for each bank group) for x4/x8 devi-
ces, and as eight banks for each bank group (2 bank groups with 4 banks each) for x16
devices. The device uses double data rate (DDR) architecture to achieve high-speed op-
eration. DDR4 architecture is essentially an 8n-prefetch architecture with an interface
designed to transfer two data words per clock cycle at the I/O pins. A single read or
write access for a device module effectively consists of a single 8n-bit-wide, four-clock-
cycle-data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-
half-clock-cycle data transfers at the I/O pins.
Read and write accesses to the device are burst-oriented. Accesses start at a selected lo-
cation and continue for a burst length of eight or a chopped burst of four in a program-
med sequence. Operation begins with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and row to be accessed (BG[1:0]
select the bank group for x4/x8, and BG0 selects the bank group for x16; BA[1:0] select
the bank, and A[17:0] select the row. See the Addressing section for more details). The
address bits registered coincident with the READ or WRITE command are used to select
the starting column location for the burst operation, determine if the auto PRECHARGE
command is to be issued (via A10), and select BC4 or BL8 mode on-the-fly (OTF) (via
A12) if enabled in the mode register.
Prior to normal operation, the device must be powered up and initialized in a prede-
fined manner. The following sections provide detailed information covering device reset
and initialization, register definition, command descriptions, and device operation.
NOTE: The use of the NOP command is allowed only when exiting maximum power
saving mode or when entering gear-down mode.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
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