MT40A512M8RH-083E Datasheet, PDF (197/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
READ Operation
Figure 128: READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8)
T0
CK_c
CK_t
T1
Ta0
Ta1
Ta2
Ta3
Tb0
Tb1
Tb2
Tb3
Tb4
Tb5
Tb6
Command READ
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
DES
Bank Group
Address
Address
BGa
Bank
col n
DQS_t
DQS_c
t_RPRE
t_RPST
DQ
AL = 10
CL = 11
RL = AL + CL
DO DO DO DO DO DO DO DO
n n+1 n+2 n+3 n+4 n+5 n+6 n+7
Time Break
Transitioning Data
Don’t Care
Notes:
1. BL8, RL = 21, AL = (CL - 1), CL = 11, Preamble = 1^tCK.
2. DO n = data-out from column n.
3. DES commands are shown for ease of illustration; other commands may be valid at
these times.
4. BL8 setting activated by either MR0[1:0] = 00 or MR0[1:0] = 01 and A12 = 1 during READ
command at T0.
5. CA parity = Disable, CS to CA latency = Disable, Read DBI = Disable.
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4gb_ddr4_dram.pdf - Rev. G 1/17 EN
197
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