MT40A512M8RH-083E Datasheet, PDF (103/365 Pages) Micron Technology – Programmable data strobe preambles

4Gb: x4, x8, x16 DDR4 SDRAM
Maximum Power-Saving Mode
Maximum Power-Saving Mode
Maximum power-saving mode provides the lowest power mode where data retention is
not required. When the device is in the maximum power-saving mode, it does not
maintain data retention or respond to any external command, except the MAXIMUM
POWER SAVING MODE EXIT command and during the assertion of RESET_n signal
LOW. This mode is more like a “hibernate mode” than a typical power-saving mode.
The intent is to be able to park the DRAM at a very low-power state; the device can be
switched to an active state via the per-DRAM addressability (PDA) mode.
Maximum Power-Saving Mode Entry
Maximum power-saving mode is entered through an MRS command. For devices with
shared control/address signals, a single DRAM device can be entered into the maxi-
mum power-saving mode using the per-DRAM addressability MRS command. Large
CS_n hold time to CKE upon the mode exit could cause DRAM malfunction; as a result,
CA parity, CAL, and gear-down modes must be disabled prior to the maximum power-
saving mode entry MRS command.
The MRS command may use both address and DQ information, as defined in the Per-
DRAM Addressability section. As illustrated in the figure below, after ^tMPED from the
mode entry MRS command, the DRAM is not responsive to any input signals except
CKE, CS_n, and RESET_n. All other inputs are disabled (external input signals may be-
come High-Z). The system will provide a valid clock until ^tCKMPE expires, at which time
clock inputs (CK) should be disabled (external clock signals may become High-Z).
Figure 44: Maximum Power-Saving Mode Entry
Ta0
Ta1
Ta2
Tb0
Tb1
Tb3
Tc0
Tc1
Tc2
Tc3
Tc4
Tc5
Tc6
Tc7
Tc8
Tc9
Tc10
Tc11
CK_c
CK_t
t_CKMPE
MR4[A1=1]
MPSM Enable)
Command DES
MRS
DES
DES
DES
t_MPED
Address
Valid
CS_n
CKE
CKE LOW makes CS_n a care; CKE LOW followed by CS_n LOW followed by CKE HIGH exits mode
RESET_n
Time Break
Don’t Care
09005aef84af6dd0
4gb_ddr4_dram.pdf - Rev. G 1/17 EN
103
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